An experimental 16-Mbit DRAM with reduced peak-current noise. - Daeje Chin; Changhyun Kim; Yunho Choi; Dong-Sun Min; Hong-Sun Hwang; Hoon Choi; Soo-In Cho; Tae-Young Chung; Chan J. Park; Yunseung Shin; Kwang Pyuk Suh; Yong E. Park (IEEE J. Solid State Circuits, 1989)

Temperature-compensation circuit techniques for high-density CMOS DRAMs. - Dong-Sun Min; Soo-In Cho; Dong Soo Jun; Dong-Jae Lee; Yongsik Seok; Daeje Chin (IEEE J. Solid State Circuits, 1992)

Variable VCC design techniques for battery-operated DRAMs. - Seung-Moon Yoo; Ejaz Haq; Seung-Hoon Lee; Yun-Ho Choi; Soo-In Cho; Nam-Soo Kang; Daeje Chin (IEEE J. Solid State Circuits, 1993)

16-Mb synchronous DRAM with 125-Mbyte/s data rate. - Yunho Choi; Myungho Kim; Hyunsoon Jang; Taejin Kim; Seung-hoon Lee; Ho-cheol Lee; Churoo Park; Siyeol Lee; Cheol-soo Kim; Soo-In Cho; Ejaz Haq; J. Karp; et al. (IEEE J. Solid State Circuits, 1994)