A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy. - Kyomin Sohn; Young-Ho Suh; Young-Jae Son; Daesik Yim; Kang-Young Kim; Dae-Gi Bae; Ted Kang; Hoon Lim; Soon-Moon Jung; Hyun-Geun Byun; Young-Hyun Jun; Kinam Kim (ISSCC, 2008)

A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme. - Yong-Cheol Bae; Joon-Young Park; Sang Jae Rhee; Seung-Bum Ko; Yonggwon Jeong; Kwang-Sook Noh; Young Hoon Son; Jaeyoun Youn; Yonggyu Chu; Hyunyoon Cho; Mijo Kim; Daesik Yim; et al. (ISSCC, 2012)

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process. - Ki Chul Chun; Yonggyu Chu; Jin-Seok Heo; Tae-Sung Kim; Soohwan Kim; Hui-Kap Yang; Mi-Jo Kim; Chang-Kyo Lee; Ju-Hwan Kim; Hyunchul Yoon; Chang-Ho Shin; Sang-uhn Cha; et al. (ISSCC, 2018)