Low Complexity Design of High Speed Parallel Decision Feedback Equalizers. - Daesun Oh; Keshab K. Parhi (ASAP, 2006)

Low Complexity Implementations of Sum-Product Algorithm for Decoding Low-Density Parity-Check Codes. - Daesun Oh; Keshab K. Parhi (SiPS, 2006)

Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check Codes. - Daesun Oh; Keshab K. Parhi (ISCAS, 2007)

Performance of Quantized Min-Sum Decoding Algorithms for Irregular LDPC Codes. - Daesun Oh; Keshab K. Parhi (ISCAS, 2007)

Optimally quantized offset min-sum algorithm for flexible LDPC decoder. - Daesun Oh; Keshab K. Parhi (ACSCC, 2008)

Nonuniformly quantized min-sum decoder architecture for low-density parity-check codes. - Daesun Oh; Keshab K. Parhi (ACM Great Lakes Symposium on VLSI, 2008)

Area efficient controller design of barrel shifters for reconfigurable LDPC decoders. - Daesun Oh; Keshab K. Parhi (ISCAS, 2008)

Low Complexity Decoder Architecture for Low-Density Parity-Check Codes. - Daesun Oh; Keshab K. Parhi (J. Signal Process. Syst., 2009)

Min-Sum Decoder Architectures With Reduced Word Length for LDPC Codes. - Daesun Oh; Keshab K. Parhi (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Low-Complexity Switch Network for Reconfigurable LDPC Decoders. - Daesun Oh; Keshab K. Parhi (IEEE Trans. Very Large Scale Integr. Syst., 2010)