An integrated time register and arithmetic circuit with combined operation for time-domain signal processing. - Daewoong Lee; Dongil Lee; Taeho Lee 001; Yong-Hun Kim; Lee-Sup Kim (ISCAS, 2015)

A 10-Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption With the Direct Feedback Method. - Yong-Hun Kim; Dongil Lee; Daewoong Lee; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 0.65-V, 11.2-Gb/s Power Noise Tolerant Source-Synchronous Injection-Locked Receiver With Direct DTLB DFE. - Dongil Lee; Yong-Hun Kim; Daewoong Lee; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks. - Hyein Shin; Jaehyeong Sim; Daewoong Lee; Lee-Sup Kim (ICCAD, 2019)

A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS. - Daewoong Lee; Dongil Lee; Yong-Hun Kim; Lee-Sup Kim (VLSI Circuits, 2019)

A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS. - Chongsoo Jung; Dongil Lee; Yong-Hun Kim; Daewoong Lee; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control. - Daewoong Lee; Dongil Lee; Yong-Hun Kim; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE With Non-Time-Overlapping Data Generation for 4: 1 CMOS Clockless Multiplexer. - Daewoong Lee; Dongil Lee; Yong-Hun Kim; Hyun-Kyu Jeon; Byung-Guk Kim; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus. - Daewoong Lee; Hye-Jung Kwon; Daehyun Kwon; Jaehyeok Baek; Chulhee Cho; Sanghoon Kim; Donggun An; Chulsoon Chang; Unhak Lim; Jiyeon Im; Wonju Sung; Hye-Ran Kim; et al. (ISSCC, 2022)

A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ. - Daewoong Lee; Jaehyeok Baek; Hye-Jung Kwon; Daehyun Kwon; Chulhee Cho; Sang-Hoon Kim; Donggun An; Chulsoon Chang; Unhak Lim; Jiyeon Im; Wonju Sung; Hye-Ran Kim; et al. (IEEE J. Solid State Circuits, 2023)

13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sanghoon Kim; Daewoong Lee; Seongyeal Yang; Gil-Young Kang; Juseop Park; Kyungho Lee; Hwan-Chul Jung; Gun-hee Cho; et al. (ISSCC, 2024)

30.3 A 24Gb 42.5Gb/s GDDR7 DRAM with Low-Power WCK Distribution, an RC-Optimized Dual-Emphasis TX, and Voltage/Time-Margin-Enhanced Power Reduction. - Sang-Hoon Kim; Jaehyeok Baek; Moon-Chul Choi; Daewoong Lee; Donggun An; Se-Mi Kim; Yeonggeun Song; Minkyo Shim; Sung-Yong Cho; Dongha Lee; Gun-hee Cho; Inwoo Jun; et al. (ISSCC, 2025)

A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sang-Hoon Kim; Daewoong Lee; Seongyeal Yang; Se-Mi Kim; Gil-Young Kang; Juseop Park; Kyung-Ho Lee; Hwan-Chul Jung; et al. (IEEE J. Solid State Circuits, 2025)