An Effective Test Pattern Generation for Testing Signal Integrity. - YongJoon Kim; Myung-Hoon Yang; Youngkyu Park; Daeyeal Lee; Sungho Kang 001 (ATS, 2006)

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology. - Daeyeal Lee; Ik Joon Chang; Sangyong Yoon; Joonsuc Jang; Dong-Su Jang; Wook-Ghee Hahn; Jong-Yeol Park; Doo-Gon Kim; Chiweon Yoon; Bong-Soon Lim; ByungJun Min; Sung-Won Yun; et al. (ISSCC, 2012)

SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm. - Dongwon Park; Daeyeal Lee; Ilgweon Kang; Sicun Gao; Bill Lin 001; Chung-Kuan Cheng (ASP-DAC, 2020)

A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT. - Chung-Kuan Cheng; Chia-Tung Ho; Daeyeal Lee; Dongwon Park (ICCAD, 2020)

Standard-Cell Scaling Framework with Guaranteed Pin-Accessibility. - Chung-Kuan Cheng; Daeyeal Lee; Dongwon Park (ISCAS, 2020)

Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules. - Dongwon Park; Daeyeal Lee; Ilgweon Kang; Chester Holtz; Sicun Gao; Bill Lin 001; Chung-Kuan Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation. - Chung-Kuan Cheng; Andrew B. Kahng; Ilgweon Kang; Minsoo Kim; Daeyeal Lee; Bill Lin 001; Dongwon Park; Mingyu Woo (ICCD, 2021)

SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC. - Daeyeal Lee; Bill Lin 001; Chung-Kuan Cheng (IEEE Embed. Syst. Lett., 2021)

SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes. - Daeyeal Lee; Dongwon Park; Chia-Tung Ho; Ilgweon Kang; Hayoung Kim; Sicun Gao; Bill Lin 001; Chung-Kuan Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT. - Chung-Kuan Cheng; Chia-Tung Ho; Daeyeal Lee; Bill Lin 001; Dongwon Park (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform. - Chung-Kuan Cheng; Chia-Tung Ho; Daeyeal Lee; Bill Lin 001 (IEEE Access, 2022)

SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing. - Daeyeal Lee; Bill Lin 001; Chung-Kuan Cheng (ACM Trans. Archit. Code Optim., 2022)

PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes. - Chung-Kuan Cheng; Andrew B. Kahng; Hayoung Kim; Minsoo Kim; Daeyeal Lee; Dongwon Park; Mingyu Woo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis. - Chung-Kuan Cheng; Chia-Tung Ho; Chester Holtz; Daeyeal Lee; Bill Lin 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Logical Reasoning Techniques for VLSI Applications - Daeyeal Lee (2022)