A Process-Variation-Tolerant On-Chip CMOS Thermometer for Auto Temperature Compensated Self-Refresh of Low-Power Mobile DRAM. - Daeyong Shim; Hyunsik Jeong; Hyunjoong Lee; Cyuyeol Rhee; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE J. Solid State Circuits, 2013)

A Sub-1.0-V On-Chip CMOS Thermometer With a Folded Temperature Sensor for Low-Power Mobile DRAM. - Hyunjoong Lee; Daeyong Shim; Cyuyeol Rhee; Mino Kim; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 1.2V 64Gb 341GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control. - Jin-Hee Cho; Jihwan Kim; Wooyoung Lee; Dong-Uk Lee; Tae-Kyun Kim 002; Heat Bit Park; Chunseok Jeong; Myeong-Jae Park; Seung Geun Baek; Seokwoo Choi; Byung Kuk Yoon; Young Jae Choi; et al. (ISSCC, 2018)

22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST. - Dong-Uk Lee; Ho Sung Cho; Jihwan Kim; Young Jun Ku; Sangmuk Oh; Chul Dae Kim; Hyun Woo Kim; Wooyoung Lee; Tae-Kyun Kim 001; Tae Sik Yun; Min Jeong Kim; SeungGyeon Lim; et al. (ISSCC, 2020)

Holistic approaches to memory solutions for the Autonomous Driving Era. - Daeyong Shim; Chunseok Jeong; Euncheol Lee; Junmo Kang; Seokcheol Yoon; Yongkee Kwon; Il Park 001; Hyun Ahn; Seonyong Cha; Jinkook Kim (ISCAS, 2022)