A load-adaptive, low switching-noise data output buffer. - Seung-Wook Lee; Daeyun Shim; Yeon-Jae Jung; Dong-Yun Lee; Chang-Hyun Kim; Wonchan Kim (ISCAS (1), 1999)

An analog synchronous mirror delay for high-speed DRAM application. - Daeyun Shim; Dong-Yun Lee; Sanghun Jung; Chang-Hyun Kim; Wonchan Kim (IEEE J. Solid State Circuits, 1999)

A dual-loop delay-locked loop using multiple voltage-controlled delay lines. - Yeon-Jae Jung; Seung-Wook Lee; Daeyun Shim; Wonchan Kim; Changhyun Kim; Soo-In Cho (IEEE J. Solid State Circuits, 2001)

A divide-by-16.5 circuit for 10-gb ethernet transceiver in 0.13-μm CMOS. - Yongsam Moon; Sang-Hyun Lee; Daeyun Shim (IEEE J. Solid State Circuits, 2005)

A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control. - Yongsam Moon; Gijung Ahn; Hoon Choi; Namhoon Kim; Daeyun Shim (ISSCC, 2006)

250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS. - Sang-Yoon Lee; Hyung-Rok Lee; Young-Ho Kwak; Woo-Seok Choi; Byoung-Joo Yoo; Daeyun Shim; Chulwoo Kim; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2011)