Design of MRAM based logic circuits and its applications. - Weisheng Zhao; Lionel Torres; Yoann Guillemenet; Luis Vitório Cargnini; Yahya Lakys; Jacques-Olivier Klein; Dafine Ravelosona; Gilles Sassatelli; Claude Chappert (ACM Great Lakes Symposium on VLSI, 2011)

High Performance SoC Design Using Magnetic Logic and Memory. - Weisheng Zhao; Lionel Torres; Luis Vitório Cargnini; Raphael Martins Brum; Yue Zhang 010; Yoann Guillemenet; Gilles Sassatelli; Yahya Lakys; Jacques-Olivier Klein; Daniel Etiemble; Dafine Ravelosona; Claude Chappert (VLSI-SoC (Selected Papers), 2011)

Crossbar architecture based on 2R complementary resistive switching memory cell. - Weisheng Zhao; Yue Zhang 010; Jacques-Olivier Klein; Damien Querlioz; Djaafar Chabi; Dafine Ravelosona; Claude Chappert; Jean-Michel Portal; Marc Bocquet; Hassen Aziza; Damien Deleruyelle; Christophe Muller (NANOARCH, 2012)

Failure and reliability analysis of STT-MRAM. - Weisheng Zhao; Yue Zhang 010; Thibaut Devolder; Jacques-Olivier Klein; Dafine Ravelosona; Claude Chappert; Pascale Mazoyer (Microelectron. Reliab., 2012)

Analytical study of complementary memristive synchronous logic gates. - Jean-Michel Portal; Mathieu Moreau; Marc Bocquet; Hassen Aziza; Damien Deleruyelle; Christophe Muller; Yue Zhang 010; Erya Deng; Jacques-Olivier Klein; Damien Querlioz; Dafine Ravelosona; Claude Chappert; et al. (NANOARCH, 2013)

Synchronous full-adder based on complementary resistive switching memory cells. - Yue Zhang 010; Erya Deng; Jacques-Olivier Klein; Damien Querlioz; Dafine Ravelosona; Claude Chappert; Weisheng Zhao; Mathieu Moreau; Jean-Michel Portal; Marc Bocquet; Hassen Aziza; Damien Deleruyelle; et al. (NEWCAS, 2013)

Emerging hybrid logic circuits based on non-volatile magnetic memories. - Weisheng Zhao; Guillaume Prenat; Jacques-Olivier Klein; Bernard Dieny; Claude Chappert; Dafine Ravelosona (NEWCAS, 2013)

Spin-electronics based logic fabrics. - Weisheng Zhao; Jacques-Olivier Klein; Zhaohao Wang; Yue Zhang 010; Nesrine Ben Romdhane; Damien Querlioz; Dafine Ravelosona; Claude Chappert (VLSI-SoC, 2013)

A low-cost built-in error correction circuit design for STT-MRAM reliability improvement. - Wang Kang 001; Weisheng Zhao; Zhaohao Wang; Yue Zhang 010; Jacques-Olivier Klein; Youguang Zhang; Claude Chappert; Dafine Ravelosona (Microelectron. Reliab., 2013)

Magnetic Adder Based on Racetrack Memory. - Hong-Phuc Trinh; Weisheng Zhao; Jacques-Olivier Klein; Yue Zhang 010; Dafine Ravelosona; Claude Chappert (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

An overview of spin-based integrated circuits. - Wang Kang 001; Weisheng Zhao; Zhaohao Wang; Jacques-Olivier Klein; Yue Zhang 010; Djaafar Chabi; Youguang Zhang; Dafine Ravelosona; Claude Chappert (ASP-DAC, 2014)

Spintronics for low-power computing. - Yue Zhang 010; Weisheng Zhao; Jacques-Olivier Klein; Wang Kang 001; Damien Querlioz; Youguang Zhang; Dafine Ravelosona; Claude Chappert (DATE, 2014)

Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires. - Nesrine Ben Romdhane; Weisheng Zhao; Yue Zhang 010; Jacques-Olivier Klein; Z. R. Wang; Dafine Ravelosona (NANOARCH, 2014)

One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories. - Wang Kang 001; Weisheng Zhao; Lun Yang; Jacques-Olivier Klein; Youguang Zhang; Dafine Ravelosona (NVMSA, 2014)

Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells. - Weisheng Zhao; Jean-Michel Portal; Wang Kang 001; Mathieu Moreau; Yue Zhang 010; Hassen Aziza; Jacques-Olivier Klein; Zhaohao Wang; Damien Querlioz; Damien Deleruyelle; Marc Bocquet; Dafine Ravelosona; et al. (J. Parallel Distributed Comput., 2014)

Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories. - Weisheng Zhao; Mathieu Moreau; Erya Deng; Yue Zhang 010; Jean-Michel Portal; Jacques-Olivier Klein; Marc Bocquet; Hassen Aziza; Damien Deleruyelle; Christophe Muller; Damien Querlioz; Nesrine Ben Romdhane; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

From device to system: cross-layer design exploration of racetrack memory. - Guangyu Sun 003; Chao Zhang 007; Hehe Li; Yue Zhang 010; Weiqi Zhang; Yizi Gu; Yinan Sun; Jacques-Olivier Klein; Dafine Ravelosona; Yongpan Liu; Weisheng Zhao; Huazhong Yang (DATE, 2015)

Perspectives of racetrack memory based on current-induced domain wall motion: From device to system. - Yue Zhang 010; Chao Zhang 007; Jacques-Olivier Klein; Dafine Ravelosona; Guangyu Sun 003; Weisheng Zhao (ISCAS, 2015)

Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM. - Wang Kang 001; Liuyang Zhang; Weisheng Zhao; Jacques-Olivier Klein; Youguang Zhang; Dafine Ravelosona; Claude Chappert (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology. - Wang Kang 001; Yue Zhang 010; Zhaohao Wang; Jacques-Olivier Klein; Claude Chappert; Dafine Ravelosona; Gefei Wang; Youguang Zhang; Weisheng Zhao (ACM J. Emerg. Technol. Comput. Syst., 2015)

Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System. - Yue Zhang 010; Chao Zhang 007; Jiang Nan; Zhizhong Zhang 004; Xueying Zhang; Jacques-Olivier Klein; Dafine Ravelosona; Guangyu Sun 003; Weisheng Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Ultra-Dense Ring-Shaped Racetrack Memory Cache Design. - Guanda Wang; Yue Zhang 010; Beibei Zhang; Bi Wu; Jiang Nan; Xueying Zhang; Zhizhong Zhang 004; Jacques-Olivier Klein; Dafine Ravelosona; Zhaohao Wang; Youguang Zhang; Weisheng Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Forecasting the outcome of spintronic experiments with Neural Ordinary Differential Equations. - Xing Chen; Flavio Abreu Araujo; Mathieu Riou; Jacob Torrejon; Dafine Ravelosona; Wang Kang 001; Weisheng Zhao; Julie Grollier; Damien Querlioz (CoRR, 2021)