Research on the Relationship between the Effect of DPA and Differential Sample Frequency. - Ruicong Ma; Daheng Yue; Shaoqing Li; Jihua Chen (DASC, 2013)

A parameterized timing-aware flip-flop merging algorithm for clock power reduction. - Chaochao Feng; Daheng Yue; Zhenyu Zhao; Zhuofan Liao (DATE, 2018)

Experimental Investigation of Charge Sharing Induced SET Depending on Transistors in Abutted Rows in 65 nm Bulk CMOS Technology. - Xiaowei He; Daheng Yue; Pengcheng Huang 003; Zhenyu Zhao (IEEE Access, 2022)

CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing. - Pengcheng Huang 003; Yaohua Wang; Zhenyu Zhao; Daheng Yue (IEEE Trans. Very Large Scale Integr. Syst., 2024)