A restricted dynamically reconfigurable architecture for low power processors. - Takeshi Hirao; Dahoo Kim; Itaru Hida; Tetsuya Asai; Masato Motomura (ReConFig, 2013)

A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator. - Itaru Hida; Dahoo Kim; Tetsuya Asai; Masato Motomura (A-SSCC, 2014)

Caching memcached at reconfigurable network interface. - Eric Shun Fukuda; Hiroaki Inoue; Takashi Takenaka; Dahoo Kim; Tsunaki Sadahisa; Tetsuya Asai; Masato Motomura (FPL, 2014)

Achieving higher performance of memcached by caching at network interface. - Eric Shun Fukuda; Hiroaki Inoue; Takashi Takenaka; Dahoo Kim; Tsunaki Sadahisa; Tetsuya Asai; Masato Motomura (FPT, 2014)

Enhancing Memcached by Caching Its Data and Functionalities at Network Interface. - Eric Shun Fukuda; Hiroaki Inoue; Takashi Takenaka; Dahoo Kim; Tsunaki Sadahisa; Tetsuya Asai; Masato Motomura (J. Inf. Process., 2015)