A Method for Guaranteeing End-to-End Delay by Mutual Cooperation between IP Routers. - Dai Yamamoto; Rie Fujita; Hideki Tode; Koso Murakami; Toshihiro Masaki (LCN, 2005)

Design and Empirical Evaluation of Control Scheme for End-to-End Delay Stabilization and Packet Loss Improvement in Broadband IP Network. - Dai Yamamoto; Hideki Tode; Toshihiro Masaki; Koso Murakami (ICCCN, 2007)

A Very Compact Hardware Implementation of the MISTY1 Block Cipher. - Dai Yamamoto; Jun Yajima; Kouichi Itoh (CHES, 2008)

Design and Experimental Evaluation of a Scheme for Maximal Improvement of End-to-End QoS in Heterogeneous IP Networks. - Dai Yamamoto; Hideki Tode; Toshihiro Masaki; Koso Murakami (IEICE Trans. Commun., 2008)

Collision-Based Power Attack for RSA with Small Public Exponent. - Kouichi Itoh; Dai Yamamoto; Jun Yajima; Wakaha Ogata (IEICE Trans. Inf. Syst., 2009)

A Very Compact Hardware Implementation of the KASUMI Block Cipher. - Dai Yamamoto; Kouichi Itoh; Jun Yajima (WISTP, 2010)

Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher. - Dai Yamamoto; Jun Yajima; Kouichi Itoh (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches. - Dai Yamamoto; Kazuo Sakiyama; Mitsugu Iwamoto; Kazuo Ohta; Takao Ochiai; Masahiko Takenaka; Kouichi Itoh (CHES, 2011)

Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher. - Dai Yamamoto; Kouichi Itoh; Jun Yajima (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs. - Dai Yamamoto; Gabriel Hospodar; Roel Maes; Ingrid Verbauwhede (SPACE, 2012)

Evaluation of ASIC Implementation of Physical Random Number Generators Using RS Latches. - Hirotaka Kokubo; Dai Yamamoto; Masahiko Takenaka; Kouichi Itoh; Naoya Torii (CARDIS, 2013)

Variety enhancement of PUF responses using the locations of random outputting RS latches. - Dai Yamamoto; Kazuo Sakiyama; Mitsugu Iwamoto; Kazuo Ohta; Masahiko Takenaka; Kouichi Itoh (J. Cryptogr. Eng., 2013)

A New Mode of Operation for Arbiter PUF to Improve Uniqueness on FPGA. - Takanori Machida; Dai Yamamoto; Mitsugu Iwamoto; Kazuo Sakiyama (FedCSIS, 2014)

Security Evaluation of Bistable Ring PUFs on FPGAs using Differential and Linear Analysis. - Dai Yamamoto; Masahiko Takenaka; Kazuo Sakiyama; Naoya Torii (FedCSIS, 2014)

A Technique Using PUFs for Protecting Circuit Layout Designs against Reverse Engineering. - Dai Yamamoto; Masahiko Takenaka; Kazuo Sakiyama; Naoya Torii (IWSEC, 2014)

Dynamic Behavior of RS latches using FIB processing and probe connection. - Naoya Torii; Dai Yamamoto; Masahiko Takenaka; Tsutomu Matsumoto (IACR Cryptol. ePrint Arch., 2014)

Implementation of double arbiter PUF and its performance evaluation on FPGA. - Takanori Machida; Dai Yamamoto; Mitsugu Iwamoto; Kazuo Sakiyama (ASP-DAC, 2015)

A new method for enhancing variety and maintaining reliability of PUF responses and its evaluation on ASICs. - Dai Yamamoto; Kazuo Sakiyama; Mitsugu Iwamoto; Kazuo Ohta; Masahiko Takenaka; Kouichi Itoh; Naoya Torii (J. Cryptogr. Eng., 2015)

Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs. - Naoya Torii; Dai Yamamoto; Tsutomu Matsumoto (TrustED@CCS, 2016)

Evaluation of Latch-Based PUFs Implemented on 40 nm ASICs. - Naoya Torii; Dai Yamamoto; Tsutomu Matsumoto (CANDAR, 2016)

ASIC implementation of random number generators using SR latches and its evaluation. - Naoya Torii; Hirotaka Kokubo; Dai Yamamoto; Kouichi Itoh; Masahiko Takenaka; Tsutomu Matsumoto (EURASIP J. Inf. Secur., 2016)

Experimental Evaluation on the Resistance of Latch PUFs Implemented on ASIC against FIB-Based Invasive Attacks. - Naoya Torii; Dai Yamamoto; Masahiko Takenaka; Tsutomu Matsumoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A Secure Framework for User-Key Provisioning to SGX Enclaves. - Takanori Machida; Dai Yamamoto; Ikuya Morikawa; Hirotaka Kokubo; Hisashi Kojima (NBiS, 2018)

A Novel Scheme of Schnorr Multi-signatures for Multiple Messages with Key Aggregation. - Rikuhiro Kojima; Dai Yamamoto; Takeshi Shimoyama; Kouichi Yasaki; Kazuaki Nimura (BWCCA, 2020)

A New Schnorr Multi-Signatures to Support Both Multiple Messages Signing and Key Aggregation. - Rikuhiro Kojima; Dai Yamamoto; Takeshi Shimoyama; Kouichi Yasaki; Kazuaki Nimura (J. Inf. Process., 2021)

Novel Deception Techniques for Malware Detection on Industrial Control Systems. - Takanori Machida; Dai Yamamoto; Yuki Unno; Hisashi Kojima (J. Inf. Process., 2021)

A Chameleon Hash-based Method for Proving Execution of Business Processes. - Tadanobu Tsunoda; Kazuaki Nimura; Dai Yamamoto; Kouichi Yasaki; Rikuhiro Kojima; Yosuke Nakamura (J. Inf. Process., 2022)