A Low Power 1.8 V 4-Bit 400-MHz Flash ADC in 0.18µ Digital CMOS. - Subhadeep Banik; Daibashish Gangopadhyay; T. K. Bhattacharyya (VLSI Design, 2006)

A 1.6 mW 5.4 GHz transformer-feedback gm-boosted current-reuse LNA in 0.18/μm CMOS. - Daibashish Gangopadhyay; Sudip Shekhar; Jeffrey S. Walling; David J. Allstot (ISCAS, 2010)

A Mode-I/Mode-III UWB LNA with programmable gain and 20 dB WLAN blocker rejection in 130nm CMOS. - Subhanshu Gupta; Daibashish Gangopadhyay; David J. Allstot (ISCAS, 2010)

Compressed sensing reconstruction: Comparative study with applications to ECG bio-signals. - Anna M. R. Dixon; Emily G. Allstot; Andrew Y. Chen; Daibashish Gangopadhyay; David J. Allstot (ISCAS, 2011)

Analog Chirp Fourier Transform for high-resolution real-time wideband RF spectrum Analysis. - Daibashish Gangopadhyay; Andrew Y. Chen; David J. Allstot (ISCAS, 2011)

Compressive sampling of EMG bio-signals. - Aabeeya Salman; Emily G. Allstot; Andrew Y. Chen; Anna M. R. Dixon; Daibashish Gangopadhyay; David J. Allstot (ISCAS, 2011)

A 2.4-GHz Extended-Range Type-I SigmaDelta Fractional-N Synthesizer With 1.8-MHz Loop Bandwidth and -110-dBc/Hz Phase Noise. - Sudip Shekhar; Daibashish Gangopadhyay; Eum Chan Woo; David J. Allstot (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 1.1µW 2.1µVRMS input noise chopper-stabilized amplifier for bio-medical applications. - Christopher J. Mandic; Daibashish Gangopadhyay; David J. Allstot (ISCAS, 2012)

A 0.8-2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass ΣΔ ADC in 0.13 µm CMOS. - Subhanshu Gupta; Daibashish Gangopadhyay; Hasnain Lakdawala; Jacques Christophe Rudell; David J. Allstot (IEEE J. Solid State Circuits, 2012)

Compressed Sensing System Considerations for ECG and EMG Wireless Biosensors. - Anna M. R. Dixon; Emily G. Allstot; Daibashish Gangopadhyay; David J. Allstot (IEEE Trans. Biomed. Circuits Syst., 2012)

Compressed Sensing Analog Front-End for Bio-Sensor Applications. - Daibashish Gangopadhyay; Emily G. Allstot; Anna M. R. Dixon; Karthik Natarajan; Subhanshu Gupta; David J. Allstot (IEEE J. Solid State Circuits, 2014)

9.4 A 2×2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation. - Renaldi Winoto; Ashkan Olyaei; Mohammad Hajirostam; Wai Lau; Xiang Gao; Arnab Mitra 002; Ovidiu Carnu; Philip Godoy; Luns Tee; Hao Li; Erdem Erdogan; Alden Wong; et al. (ISSCC, 2016)