PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM. - Tatsuya Kubo; Daichi Tokuda; Lei Qu; Ting Cao; Shinya Takamaeda-Yamazaki (IEEE Comput. Archit. Lett., 2025)

MVDRAM: Enabling GeMV Execution in Unmodified DRAM for Low-Bit LLM Acceleration. - Tatsuya Kubo; Daichi Tokuda; Tomoya Nagatani; Masayuki Usui; Lei Qu; Ting Cao; Shinya Takamaeda-Yamazaki (CoRR, 2025)

DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination. - Daichi Tokuda; Shinya Takamaeda-Yamazaki (ACM Trans. Reconfigurable Technol. Syst., 2025)