A Parametric Study of Scalable Interconnects on FPGAs. - Daihan Wang; Hiroki Matsutani; Masato Yoshimi; Michihiro Koibuchi; Hideharu Amano (ERSA, 2006)

A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. - Daihan Wang; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (FPL, 2007)

A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs. - Daihan Wang; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2007)

Run-time power gating of on-chip routers using look-ahead routing. - Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano; Daihan Wang (ASP-DAC, 2008)

A link removal methodology for Networks-on-Chip on reconfigurable systems. - Daihan Wang; Hiroki Matsutani; Hideharu Amano; Michihiro Koibuchi (FPL, 2008)

Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. - Hiroki Matsutani; Michihiro Koibuchi; Daihan Wang; Hideharu Amano (NOCS, 2008)

A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs. - Daihan Wang; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2009)

A Dynamic Link-Width Optimization for Network-on-Chip. - Daihan Wang; Michihiro Koibuchi; Tomohiro Yoneda; Hiroki Matsutani; Hideharu Amano (RTCSA (2), 2011)