Identification and authentication of integrated circuits. - Blaise Gassend; Daihyun Lim; Dwaine E. Clarke; Marten van Dijk; Srinivas Devadas (Concurr. Pract. Exp., 2004)

Extracting secret keys from integrated circuits. - Daihyun Lim; Jae W. Lee; Blaise Gassend; G. Edward Suh; Marten van Dijk; Srinivas Devadas (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Variation. - Duane S. Boning; Karthik Balakrishnan; Hong Cai; Nigel Drego; Ali Farahanchi; Karen Gettings; Daihyun Lim; Ajay Somani; Hayden Taylor; Daniel Truque; Xiaolin Xie (ISQED, 2007)

A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology. - Choongyeun Cho; Daeik D. Kim; Jonghae Kim; Jean-Olivier Plouchart; Daihyun Lim; Sangyeun Cho; Robert Trzcinski (ISQED, 2007)

A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOS. - Daeik D. Kim; Jonghae Kim; Jean-Olivier Plouchart; Choongyeun Cho; Weipeng Li; Daihyun Lim; Robert Trzcinski; Mahender Kumar; Christine Norris; David Ahlgren (ISSCC, 2007)

Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS. - Daihyun Lim; Jonghae Kim; Jean-Olivier Plouchart; Choongyeun Cho; Daeik D. Kim; Robert Trzcinski; Duane S. Boning (ISSCC, 2007)

Early prediction of product performance and yield via technology benchmark. - Choongyeun Cho; Daeik D. Kim; Jonghae Kim; Daihyun Lim; Sangyeun Cho (CICC, 2008)

Characterization of process variability and robust optimization of analog circuits. - Daihyun Lim (2008)

A Silicon Photonic Transceiver and Hybrid Tunable Laser for 64 Gbaud Coherent Communication. - Ari Novack; Matthew Streshinsky; Tam N. Huynh; Tal Galfsky; Hang Guan; Yang Liu 178; Yangjin Ma; Ruizhi Shi; Alexandre Horth; Yaojia Chen; Amir Hanjani; Jose Roman; et al. (OFC, 2018)

A 6V Swing 3.6% THD >40GHz Driver with 4.5× Bandwidth Extension for a 272Gb/s Dual-Polarization 16-QAM Silicon Photonic Transmitter. - Abdelrahman H. Ahmed; Daihyun Lim; Abdellatif Elmoznine; Yangjin Ma; Tam N. Huynh; Christopher Williams 003; Leonardo Vera; Yang Liu 178; Ruizhi Shi; Matthew Streshinsky; Ari Novack; Ran Ding; et al. (ISSCC, 2019)

An All-Silicon Transmitter with Co-Designed Modulator and DC-Coupled Driver. - Yangjin Ma; Christopher Williams 003; Mostafa Gamal Ahmed; Abdellatif Elmoznine; Daihyun Lim; Yang Liu 178; Ruizhi Shi; Tam N. Huynh; Jose Roman; Abdelrahman H. Ahmed; Leonardo Vera; Yaojia Chen; et al. (OFC, 2019)

A Dual-Polarization Silicon-Photonic Coherent Transmitter Supporting 552 Gb/s/wavelength. - Abdelrahman H. Ahmed; Abdellatif Elmoznine; Daihyun Lim; Yangjin Ma; Alexander V. Rylyakov; Sudip Shekhar (IEEE J. Solid State Circuits, 2020)

A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications. - Hyun-A. Ahn; Yoo-Chang Sung; Yong-Hun Kim; Janghoo Kim; Kihan Kim; Donghun Lee; Young-Gil Go; Jae-Woo Lee; Jae-Woo Jung; Yong-Hyun Kim; Garam Choi; Jun-Seo Park; et al. (A-SSCC, 2023)

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process. - IkJoon Choi; Seunghwan Hong; Kihyun Kim; Jeongsik Hwang; Seunghan Woo; Young-Sang Kim; Cheongryong Cho; Eun-Young Lee; Hun-Jae Lee; Min-Su Jung; Hee-Yun Jung; Ju-Seong Hwang; et al. (ISSCC, 2024)

A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications. - Hyun-A. Ahn; Yoo-Chang Sung; Yong-Hun Kim; Janghoo Kim; Kihan Kim; Dong-Hun Lee; Young-Gil Go; Jae-Woo Lee; Jae-Woo Jung; Yong-Hyun Kim; Garam Choi; Jun-Seo Park; et al. (IEEE J. Solid State Circuits, 2024)

A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration and AC-Coupled Transceiver Equalization in a 5th-Generation 10nm DRAM Process. - Jin-Hyeok Baek; Jang-Hoo Kim; Yoo-Chang Sung; Jae-Woo Jeong; Jin-Kwan Park; Hyun-Kyu Oh; Bo-Hyeon Lee; Dong-Wan Ko; Tae-Seob Oh; Seung-Gi Hong; Chang-Ki Kwon; Daihyun Lim; et al. (ISSCC, 2025)