Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements. - Masato Sakurai; Kiichi Niitsu; Naohiro Harigai; Daiki Hirabayashi; Daiki Oki; Takahiro J. Yamaguchi; Haruo Kobayashi 001 (ISOCC, 2011)

Multi-bit sigma-delta TDC architecture with self-calibration. - Satoshi Uemori; Masamichi Ishii; Haruo Kobayashi 001; Yuta Doi; Osamu Kobayashi; Tatsuji Matsuura; Kiichi Niitsu; Yuta Arakawa; Daiki Hirabayashi; Yuji Yano; Tatsuhiro Gake; Nobukazu Takai; et al. (APCCAS, 2012)

A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS. - Kiichi Niitsu; Masato Sakurai; Naohiro Harigai; Daiki Hirabayashi; Takahiro J. Yamaguchi; Haruo Kobayashi 001 (ASP-DAC, 2012)

A clock jitter reduction circuit using gated phase blending between self-delayed clock edges. - Kiichi Niitsu; Naohiro Harigai; Daiki Hirabayashi; Daiki Oki; Masato Sakurai; Osamu Kobayashi; Takahiro J. Yamaguchi; Haruo Kobayashi 001 (VLSIC, 2012)

Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. - Kiichi Niitsu; Naohiro Harigai; Daiki Hirabayashi; Daiki Oki; Masato Sakurai; Osamu Kobayashi; Takahiro J. Yamaguchi; Haruo Kobayashi 001 (ASP-DAC, 2013)

Multi-bit Sigma-Delta TDC Architecture with Improved Linearity. - Satoshi Uemori; Masamichi Ishii; Haruo Kobayashi 001; Daiki Hirabayashi; Yuta Arakawa; Yuta Doi; Osamu Kobayashi; Tatsuji Matsuura; Kiichi Niitsu; Yuji Yano; Tatsuhiro Gake; Takahiro J. Yamaguchi; et al. (J. Electron. Test., 2013)

A CMOS PWM Transceiver Using Self-Referenced Edge Detection. - Kiichi Niitsu; Yusuke Osawa; Naohiro Harigai; Daiki Hirabayashi; Osamu Kobayashi; Takahiro J. Yamaguchi; Haruo Kobayashi 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)