An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process. - Yuejun Zhang; Dailu Ding; Zhao Pan 001; Pengjun Wang; Qiaoyan Yu (Microelectron. J., 2018)

A 0.1-pJ/b and ACF <0.04 Multiple-Valued PUF for Chip Identification Using Bit-Line Sharing Strategy in 65-nm CMOS. - Yuejun Zhang; Zhao Pan 001; Pengjun Wang; Dailu Ding; Qiaoyan Yu (IEEE Trans. Very Large Scale Integr. Syst., 2019)