A Layout Area Reduction of Basic Logic Element by Using a Neuron CMOS Type 4-input Variable Logic Circuit. - Shoma Ito; Hisaya Sawada; Hirotaka Furukawa; Naruaki Hokari; Daishi Nishiguchi; Masaaki Fukuhara (TENCON, 2023)

A Neuron CMOS Type Full Subtractor with Floating Gate Calibration Circuit. - Hirotaka Furukawa; Hisaya Sawada; Naruaki Hokari; Tatsuya Hasegawa; Daishi Nishiguchi; Masaaki Fukuhara (ISPACS, 2024)

A Minimum Value Determination Circuit Using a Neuron CMOS WTA with FGC Circuit. - Naruaki Hokari; Hisaya Sawada; Hirotaka Furukawa; Tatsuya Hasegawa; Daishi Nishiguchi; Masaaki Fukuhara (ISPACS, 2024)

Low-Power Hamming Distance Detection Circuit Using Cross-Coupled Electronic Neuron. - Daishi Nishiguchi; Masaaki Fukuhara; Mitsutoshi Yahara; Kuniaki Fujimoto (TENCON, 2024)

Enhancing the Readout Speed of NP-H-CAM Using Clocked CMOS Inverters. - Hisaya Sawada; Hirotaka Furukawa; Naruaki Hokari; Daishi Nishiguchi; Yujiro Harada; Masaaki Fukuhara (TENCON, 2024)