Improvement of passive elements for wearable haptic displays. - Sadao Kawamura; Katsuya Kanaoka; Yuichiro Nakayama; Jinwoo Jeon; Daisuke Fujimoto (ICRA, 2003)

A 6-bit arbitrary digital noise emulator in 65nm CMOS technology. - Tetsuro Matsuno; Daisuke Fujimoto; Daisuke Kosaka; Naoyuki Hamanishi; Ken Tanabe; Masazumi Shiochi; Makoto Nagata (CICC, 2009)

An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology. - Tetsuro Matsuno; Daisuke Fujimoto; Daisuke Kosaka; Naoyuki Hamanishi; Ken Tanabe; Masazumi Shiochi; Makoto Nagata (IEICE Trans. Electron., 2010)

A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. - Daisuke Fujimoto; Makoto Nagata; Toshihiro Katashita; Akihiro T. Sasaki; Yohei Hori; Akashi Satoh (HOST, 2011)

A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation. - Daisuke Fujimoto; Toshihiro Katashita; Akihiko Sasaki; Yohei Hori; Akashi Satoh; Makoto Nagata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor. - Noriyuki Miura; Daisuke Fujimoto; Rie Korenaga; Kohei Matsuda; Makoto Nagata (A-SSCC, 2014)

On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips. - Makoto Nagata; Daisuke Fujimoto; Noriyuki Miura (ATS, 2014)

Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. - Shivam Bhasin; Jean-Luc Danger; Tarik Graba; Yves Mathieu; Daisuke Fujimoto; Makoto Nagata (ES4CPS@DATE, 2014)

Side-channel leakage on silicon substrate of CMOS cryptographic chip. - Daisuke Fujimoto; Daichi Tanaka; Noriyuki Miura; Makoto Nagata; Yu-ichi Hayashi; Naofumi Homma; Shivam Bhasin; Jean-Luc Danger (HOST, 2014)

12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. - Noriyuki Miura; Shiro Dosho; Satoshi Takaya; Daisuke Fujimoto; Takuya Kiriyama; Hiroyuki Tezuka; Takuji Miki; Hiroto Yanagawa; Makoto Nagata (ISSCC, 2014)

A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor. - Noriyuki Miura; Daisuke Fujimoto; Daichi Tanaka; Yu-ichi Hayashi; Naofumi Homma; Takafumi Aoki; Makoto Nagata (VLSIC, 2014)

EM Attack Is Non-Invasive? - Design Methodology and Validity Verification of EM Attack Sensor. - Naofumi Homma; Yu-ichi Hayashi; Noriyuki Miura; Daisuke Fujimoto; Daichi Tanaka; Makoto Nagata; Takafumi Aoki (IACR Cryptol. ePrint Arch., 2014)

Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. - Daisuke Fujimoto; Noriyuki Miura; Makoto Nagata; Yu-ichi Hayashi; Naofumi Homma; Takafumi Aoki; Yohei Hori; Toshihiro Katashita; Kazuo Sakiyama; Thanh-Ha Le; Julien Bringer; Pirouz Bazargan-Sabet; et al. (IEICE Trans. Electron., 2014)

A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor. - Daisuke Fujimoto; Noriyuki Miura; Yu-ichi Hayashi; Naofumi Homma; Takafumi Aoki; Makoto Nagata (ASP-DAC, 2015)

A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement. - Daisuke Fujimoto; Makoto Nagata; Shivam Bhasin; Jean-Luc Danger (ASP-DAC, 2015)

EM attack sensor: concept, circuit, and design-automation methodology. - Noriyuki Miura; Daisuke Fujimoto; Makoto Nagata; Naofumi Homma; Yu-ichi Hayashi; Takafumi Aoki (DAC, 2015)

A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan. - Noriyuki Miura; Shiro Dosho; Hiroyuki Tezuka; Takuji Miki; Daisuke Fujimoto; Takuya Kiriyama; Makoto Nagata (IEEE J. Solid State Circuits, 2015)

A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation. - Sho Endo; Yang Li 001; Naofumi Homma; Kazuo Sakiyama; Kazuo Ohta; Daisuke Fujimoto; Makoto Nagata; Toshihiro Katashita; Jean-Luc Danger; Takafumi Aoki (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Laser irradiation on EEPROM sense amplifiers enhances side-channel leakage of read bits. - Junichi Sakamoto; Daisuke Fujimoto; Tsutomu Matsumoto (AsianHOST, 2016)

How to design hardware prime field multipliers for bilinear pairing. - Daisuke Fujimoto; Yusuke Nagahama; Tsutomu Matsumoto (ISOCC, 2016)

A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version). - Daisuke Fujimoto; Shivam Bhasin; Makoto Nagata; Jean-Luc Danger (IACR Cryptol. ePrint Arch., 2016)

Protecting cryptographic integrated circuits with side-channel information. - Makoto Nagata; Daisuke Fujimoto; Noriyuki Miura; Naofumi Homma; Yu-ichi Hayashi; Kazuo Sakiyama (IEICE Electron. Express, 2017)

Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks. - Naofumi Homma; Yu-ichi Hayashi; Noriyuki Miura; Daisuke Fujimoto; Makoto Nagata; Takafumi Aoki (J. Cryptol., 2017)

A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs. - Daisuke Fujimoto; Shota Nin; Yu-ichi Hayashi; Noriyuki Miura; Makoto Nagata; Tsutomu Matsumoto (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Low-Latency Pairing Processor Architecture Using Fully-Unrolled Quotient Pipelining Montgomery Multiplier. - Junichi Sakamoto; Yusuke Nagahama; Daisuke Fujimoto; Yota Okuaki; Tsutomu Matsumoto (AsianHOST, 2019)

Design Considerations for EM Pulse Fault Injection. - Arthur Beckers; Masahiro Kinugawa; Yu-ichi Hayashi; Daisuke Fujimoto; Josep Balasch; Benedikt Gierlichs; Ingrid Verbauwhede (CARDIS, 2019)

Fundamental Study on the Effects of Connector Torque Value on the Change of Inductance at the Contact Boundary. - Daisuke Fujimoto; Takashi Narimatsu; Yu-ichi Hayashi (IEICE Trans. Electron., 2019)

Electromagnetic Information Extortion from Electronic Devices Using Interceptor and Its Countermeasure. - Masahiro Kinugawa; Daisuke Fujimoto; Yu-ichi Hayashi (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019)

How to Code Data Integrity Verification Secure Against Single-Spot-Laser-Induced Instruction Manipulation Attacks. - Junichi Sakamoto; Shungo Hayashi; Daisuke Fujimoto; Tsutomu Matsumoto (AICCSA, 2020)

Comparison of Pearson correlation coefficient and distance correlation in Correlation Power Analysis on Digital Multiplier. - Jurica Kundrata; Daisuke Fujimoto; Yu-ichi Hayashi; Adrijan Baric (MIPRO, 2020)

Laser-Induced Controllable Instruction Replacement Fault Attack. - Junichi Sakamoto; Daisuke Fujimoto; Tsutomu Matsumoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)

Efficient Algorithms for Sign Detection in RNS Using Approximate Reciprocals. - Shinichi Kawamura; Yuichi Komano; Hideo Shimizu; Saki Osuka; Daisuke Fujimoto; Yu-ichi Hayashi; Kentaro Imafuku (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Constructing software countermeasures against instruction manipulation attacks: an approach based on vulnerability evaluation using fault simulator. - Junichi Sakamoto; Shungo Hayashi; Daisuke Fujimoto; Tsutomu Matsumoto (Clust. Comput., 2022)

Fundamental Study on Detecting Hardware Trojans in Printed Circuit Boards Using Ring Oscillators. - Koki Abe; Daisuke Fujimoto; Yuichi Hayashi (EMC Compo, 2024)

Current Consumption Modeling of Logic Cells Based on Measurements for Side-channel Attack Simulation. - Daisuke Fujimoto; Taichi Sato; Yuichi Hayashi (EMC Compo, 2024)

Controlling Faulty Byte Outputs with IEMI against Cryptographic ICs. - Hikaru Nishiyama; Daisuke Fujimoto; Yuichi Hayashi (EMC Compo, 2024)

High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications. - Junichi Sakamoto; Daisuke Fujimoto; Riku Anzai; Naoki Yoshida; Tsutomu Matsumoto (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Current consumption model for more efficient side-channel tolerant design at FPGA design stage. - Daisuke Fujimoto; Yuichi Hayashi (ASP-DAC, 2025)

Amplifying Electromagnetic Leakage by Hardware Trojans Through Cable Geometry Manipulation. - Hayato Ide; Shohei Matsumoto; Taiki Kitazawa; Shugo Kaji; Daisuke Fujimoto; Takashi Kasuga; Yuichi Hayashi (HOST, 2025)

Detection of Hardware Trojans Using a Capacitance Sensor Focused on Parasitic Coupling Between Wires. - Rikuo Haga; Shugo Kaji; Daisuke Fujimoto; Yuichi Hayashi (NewCAS, 2025)

Remote fault injection attack against cryptographic modules via intentional electromagnetic interference from an antenna. - Hikaru Nishiyama; Daisuke Fujimoto; Yuichi Hayashi (J. Cryptogr. Eng., 2025)

CHIRP: Compact and High-Performance FPGA Implementation of Unified Hardware Accelerators for Ring-Binary-LWE-based PQC. - Tianyou Bao; Pengzhou He; Daisuke Fujimoto; Yuichi Hayashi; Jiafeng Xie (ACM Trans. Reconfigurable Technol. Syst., 2025)