A novel third order Delta Sigma Modulator with one opamp shared among three integrator stages. - Daisuke Kanemoto; Toru Ido; Kenji Taniguchi 001 (IEICE Electron. Express, 2008)

A 7.5mW 101dB SNR low-power high-performance audio delta-sigma modulator utilizing opamp sharing technique. - Daisuke Kanemoto; Toru Ido; Kenji Taniguchi 001 (ISOCC, 2011)

A Novel 100ppm/°C current reference for ultra-low-power subthreshold applications. - Indika U. K. Bogoda Appuhamylage; Daisuke Kanemoto; Kenji Taniguchi 001 (IEICE Electron. Express, 2011)

A third order delta-sigma modulator employing shared opamp technique for WCDMA on 0.18um CMOS. - Ghazal A. Fahmy; Daisuke Kanemoto; Haruichi Kanaya; Keiji Yoshida; Ramesh K. Pokharel; Awinash Anand (IEICE Electron. Express, 2011)

A small die area and high linearity 10-bit capacitive three-level DAC. - Keigo Oshiro; Daisuke Kanemoto; Haruichi Kanaya; Ramesh K. Pokharel; Keiji Yoshida (APCCAS, 2012)

A novel high-precision DAC utilizing tribonacci series. - Kazuya Hokazono; Daisuke Kanemoto; Haruichi Kanaya; Ramesh K. Pokharel; Keiji Yoshida (IEICE Electron. Express, 2012)

A novel RC time constant tuning technique utilizing programmable current sources for continuous-time delta-sigma modulators. - Daisuke Kanemoto; Yu Tamura; Indika U. K. Bogoda Appuhamylage; Toshimasa Matsuoka; Kenji Taniguchi 001 (IEICE Electron. Express, 2012)

A High Dynamic Range and Low Power Consumption Audio Delta-Sigma Modulator with Opamp Sharing Technique among Three Integrators. - Daisuke Kanemoto; Toru Ido; Kenji Taniguchi 001 (IEICE Trans. Electron., 2012)

A self-biasing class-E power amplifier for 5-GHz constant envelope modulation system. - Yuki Yamashita; Daisuke Kanemoto; Haruichi Kanaya; Ramesh K. Pokharel; Keiji Yoshida (IEICE Electron. Express, 2013)

High frequency ring oscillator using capacitor based level shift circuits. - Takahide Sato; Takeshi Nagata; Daisuke Kanemoto (APCCAS, 2014)

A design methodology for SAR ADC optimal redundancy bit. - Toru Okazaki; Daisuke Kanemoto; Ramesh K. Pokharel; Keiji Yoshida; Haruichi Kanaya (IEICE Electron. Express, 2014)

A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications. - Daisuke Kanemoto; Keigo Oshiro; Keiji Yoshida; Haruichi Kanaya (ASP-DAC, 2015)

Effect of Linearity Enhancement in A/D Conversion for Single Carrier Transmission Systems. - Osamu Muta; Daisuke Kanemoto; Syota Fukushige; Hiroshi Furukawa (VTC Spring, 2015)

Framework of Applying Independent Component Analysis After Compressed Sensing for Electroencephalogram Signals. - Daisuke Kanemoto; Shun Katsumata; Masao Aihara; Makoto Ohki (BioCAS, 2018)

Applying Outlier Detection and Independent Component Analysis for Compressed Sensing EEG Measurement Framework. - Shun Katsumata; Daisuke Kanemoto; Makoto Ohki (BioCAS, 2019)

Sub-0.1V Input, Low-Voltage CMOS Driver Circuit for Multi-Stage Switched Capacitor Voltage Boost Converter. - Masaya Nishi; Yuichiro Nakazawa; Kaori Matsumoto; Nobutaka Kuroki; Masahiro Numa; Ryo Matsuzuka; Osamu Maida; Daisuke Kanemoto; Tetsuya Hirose (ICECS, 2019)

A 34-mV Startup Ring Oscillator Using Stacked Body Bias Inverters for Extremely Low-Voltage Thermoelectric Energy Harvesting. - Masaya Nishi; Kaori Matsumoto; Nobutaka Kuroki; Masahiro Numa; Hikaru Sebe; Ryo Matsuzuka; Osamu Maida; Daisuke Kanemoto; Tetsuya Hirose (NEWCAS, 2020)

An 11.8 nA ultra-low power active diode using a hysteresis common gate comparator for low-power energy harvesting systems. - Kaori Matsumoto; Hiroki Asano; Yuichiro Nakazawa; Nobutaka Kuroki; Masahiro Numa; Osamu Maida; Daisuke Kanemoto; Tetsuya Hirose (IEICE Electron. Express, 2020)

Compressed Sensing Framework Applying Independent Component Analysis after Undersampling for Reconstructing Electroencephalogram Signals. - Daisuke Kanemoto; Shun Katsumata; Masao Aihara; Makoto Ohki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)

A 35-mV supply ring oscillator consisting of stacked body bias inverters for extremely low-voltage LSIs. - Masaya Nishi; Kaori Matsumoto; Nobutaka Kuroki; Masahiro Numa; Hikaru Sebe; Ryo Matsuzuka; Osamu Maida; Daisuke Kanemoto; Tetsuya Hirose (IEICE Electron. Express, 2021)

Applying K-SVD Dictionary Learning for EEG Compressed Sensing Framework with Outlier Detection and Independent Component Analysis. - Kotaro Nagai; Daisuke Kanemoto; Makoto Ohki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Sub-50-mV Charge Pump and its Driver for Extremely Low-Voltage Thermal Energy Harvesting. - Hikaru Sebe; Daisuke Kanemoto; Tetsuya Hirose (ISCAS, 2022)

Image Quality Improvement for Capsule Endoscopy Based on Compressed Sensing with K-SVD Dictionary Learning. - Yuuki Harada; Daisuke Kanemoto; Takahiro Inoue; Osamu Maida; Tetsuya Hirose (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

Compressed Sensing EEG Measurement Technique with Normally Distributed Sampling Series. - Yuki Okabe; Daisuke Kanemoto; Osamu Maida; Tetsuya Hirose (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

Sub-30-mV-Supply, Fully Integrated Ring Oscillator Consisting of Recursive Stacking Body-Bias Inverters for Extremely Low-Voltage Energy Harvesting. - Hikaru Sebe; Tomohisa Okumura; Shintaro Sumi; Daisuke Kanemoto; Po-Hung Chen; Tetsuya Hirose (ESSCIRC, 2023)

A Programmable Differential Bandgap Reference for Ultra-Low-Power IoT Edge Node Devices. - Yoshinori Itotagawa; Koma Atsumi; Hikaru Sebe; Daisuke Kanemoto; Tetsuya Hirose (ISCAS, 2023)

EEG Measurements with Compressed Sensing Utilizing EEG Signals as the Basis Matrix. - Daisuke Kanemoto; Tetsuya Hirose (ISCAS, 2023)

Random Undersampling Wireless EEG Measurement Device using a Small TEG. - Takuya Miyata; Daisuke Kanemoto; Tetsuya Hirose (ISCAS, 2023)

Utilizing Previously Acquired BSBL Algorithm Parameters in the Compressed Sensing Framework for EEG Measurements. - Takuya Miyata; Daisuke Kanemoto; Tetsuya Hirose (ICCE, 2024)

Noise-Masking Cryptosystem Using Watermark and Chain Generation for EEG Measurement with Compressed Sensing. - Ryota Tsunaga; Daisuke Kanemoto; Tetsuya Hirose (ICCE, 2024)

Reducing Power Consumption in LNA by Utilizing EEG Signals as Basis Matrix in Compressed Sensing. - Riku Matsubara; Daisuke Kanemoto; Tetsuya Hirose (ISCAS, 2024)

Programmable Differential Bandgap Reference Circuit for Ultra-Low-Power CMOS LSIs. - Yoshinori Itotagawa; Koma Atsumi; Hikaru Sebe; Daisuke Kanemoto; Tetsuya Hirose (IEICE Trans. Electron., 2024)

Sub-60-mV Charge Pump and its Driver Circuit for Extremely Low-Voltage Thermoelectric Energy Harvesting. - Hikaru Sebe; Daisuke Kanemoto; Tetsuya Hirose (IEICE Trans. Electron., 2024)

Low quiescent current LDO with FBPEC to improve PSRR specific frequency band for wearable EEG recording devices. - Kenji Mii; Daisuke Kanemoto; Tetsuya Hirose (ASP-DAC, 2025)

Ultra Low-power Capacitively-coupled Chopper Amplifier Focusing on the Sparsity of Compressed Sensing for EEG Recording. - Kenji Mii; Daisuke Kanemoto; Tetsuya Hirose (ASP-DAC, 2025)

Design Guidelines for Noise in a Low-Noise Amplifier Using EEG Signals as a Basis Matrix in Compressed Sensing System. - Riku Matsubara; Daisuke Kanemoto; Tetsuya Hirose (ICCE, 2025)

Noise-Masking Cryptosystem Using Watermark and Chain Generation for EEG Measurement with Compressed Sensing. - Tomoya Yamamoto; Daisuke Kanemoto; Tetsuya Hirose (ICCE, 2025)

Development of Low-power and High-accuracy Wireless EEG Transmission System Using Compressed Sensing with an EEG Basis. - Daisuke Kanemoto; Eichi Takimoto; Tetsuya Hirose (ISCAS, 2025)

Low-power and Low-noise Amplifier with Intermittent Operation for Compressed Sensing in EEG Measurement Systems. - Kenji Mii; Daisuke Kanemoto; Tetsuya Hirose (ISCAS, 2025)

Sub-50-mV Static Flip-Flop Consisting of Recursive Stacking Body-Bias Logic Gates for Extremely Low-Voltage VLSIs. - Shintaro Sumi; Hikaru Sebe; Daisuke Kanemoto; Tetsuya Hirose (ISCAS, 2025)