Multi-axis Force Sensor Using Piezoresistors and a Plate-Like Structure. - Hirotoshi Eguchi; Hiroshi Yamazaki; Jun-ichi Takahashi; Daisuke Kosaka; Shoji Matsumoto; Takashi Akahori; Eiichi Ohta; Yuhji Kimura; Kouji Izumi (IROS, 1988)

Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation. - Daisuke Kosaka; Makoto Nagata (ASP-DAC, 2006)

Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation. - Daisuke Kosaka; Makoto Nagata; Yoshitaka Murasaka; Atsushi Iwata (CICC, 2007)

Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits. - Daisuke Kosaka; Makoto Nagata; Yoshitaka Murasaka; Atsushi Iwata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Chip-Level Substrate Coupling Analysis with Reference Structures for Verification. - Daisuke Kosaka; Makoto Nagata; Yoshitaka Murasaka; Atsushi Iwata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design. - Daisuke Kosaka; Yoji Bando; Goichi Yokomizo; Kunihiko Tsuboi; Ying Shiun Li; Shen Lin; Makoto Nagata (CICC, 2009)

A 6-bit arbitrary digital noise emulator in 65nm CMOS technology. - Tetsuro Matsuno; Daisuke Fujimoto; Daisuke Kosaka; Naoyuki Hamanishi; Ken Tanabe; Masazumi Shiochi; Makoto Nagata (CICC, 2009)

An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology. - Tetsuro Matsuno; Daisuke Fujimoto; Daisuke Kosaka; Naoyuki Hamanishi; Ken Tanabe; Masazumi Shiochi; Makoto Nagata (IEICE Trans. Electron., 2010)

Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits. - Tetsuro Matsuno; Daisuke Kosaka; Makoto Nagata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)