A four-input beam-forming downconverter for adaptive antennas. - Takafumi Yamaji; Daisuke Kurose; Osamu Watanabe 003; Shuichi Obayashi; Tetsuro Itakura (IEEE J. Solid State Circuits, 2003)

Capacitance Mismatch Evaluation for Low-power Pipeline ADC Design. - Tomohiko Ito; Takafumi Yamaji; Daisuke Kurose; Tetsuro Itakura (IEICE Electron. Express, 2004)

A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter. - Tomohiko Ito; Takeshi Ueno; Daisuke Kurose; Takafumi Yamaji; Tetsuro Itakura (IEICE Electron. Express, 2005)

Low-Power Design of 10-bit 80-MSPS Pipeline ADCs. - Tomohiko Ito; Daisuke Kurose; Takeshi Ueno; Takafumi Yamaji; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. - Daisuke Kurose; Tomohiko Ito; Takeshi Ueno; Takafumi Yamaji; Tetsuro Itakura (IEEE J. Solid State Circuits, 2006)

55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers. - Tomohiko Ito; Daisuke Kurose; Takeshi Ueno; Takafumi Yamaji; Tetsuro Itakura (IEICE Trans. Electron., 2008)

A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals. - Akihide Sai; Daisuke Kurose; Takafumi Yamaji; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters. - Takeshi Ueno; Tomohiko Ito; Daisuke Kurose; Takafumi Yamaji; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A 2Gb/s-throughput CMOS transceiver chipset with in-package antenna for 60GHz short-range wireless communication. - Toshiya Mitomo; Yukako Tsutsumi; Hiroaki Hoshino; Masahiro Hosoya; Tong Wang 018; Yuta Tsubouchi; Ryoichi Tachibana; Akihide Sai; Yuka Kobayashi; Daisuke Kurose; Tomohiko Ito; Koichiro Ban; et al. (ISSCC, 2012)

A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS. - Daisuke Miyashita; Kenichi Agawa; Hirotsugu Kajihara; Kenichi Sami; Masaomi Iwanaga; Yosuke Ogasawara; Tomohiko Ito; Daisuke Kurose; Naotaka Koide; Toru Hashimoto; Hiroki Sakurai; Takafumi Yamaji; et al. (VLSIC, 2012)

A 2-Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60-GHz Short-Range Wireless Communication. - Toshiya Mitomo; Yukako Tsutsumi; Hiroaki Hoshino; Masahiro Hosoya; Tong Wang 018; Yuta Tsubouchi; Ryoichi Tachibana; Akihide Sai; Yuka Kobayashi; Daisuke Kurose; Tomohiko Ito; Koichiro Ban; et al. (IEEE J. Solid State Circuits, 2012)

Correction to "A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication". - Toshiya Mitomo; Yukako Tsutsumi; Hiroaki Hoshino; Masahiro Hosoya; Tong Wang 018; Yuta Tsubouchi; Ryoichi Tachibana; Akihide Sai; Yuka Kobayashi; Daisuke Kurose; Tomohiko Ito; Koichiro Ban; et al. (IEEE J. Solid State Circuits, 2013)

A power supply noise cancellation scheme for a 2.24-GHz 6-bit current-steering DAC. - Kei Shiraishi; Daisuke Kurose; Masanori Furuta; Tetsuro Itakura (ISCAS, 2014)

A power-scalable zero-crossing-based amplifier using inverter-based zero-crossing detector with CMFB. - Junya Matsuno; Daisuke Kurose; Tomohiko Sugimoto; Hirotomo Ishii; Masanori Furuta; Tetsuro Itakura (ISCAS, 2016)

28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique. - Kentaro Yoshioka; Tomohiko Sugimoto; Naoya Waki; Sinnyoung Kim; Daisuke Kurose; Hirotomo Ishii; Masanori Furuta; Akihide Sai; Tetsuro Itakura (ISSCC, 2017)

A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique. - Kentaro Yoshioka; Hiroshi Kubota; Tomonori Fukushima; Satoshi Kondo; Tuan Thanh Ta; Hidenori Okuni; Kaori Watanabe; Yoshinari Ojima; Katsuyuki Kimura; Sohichiroh Hosoda; Yutaka Ota; Tomohiro Koizumi; et al. (ISSCC, 2018)

A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 × 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC. - Kentaro Yoshioka; Hiroshi Kubota; Tomonori Fukushima; Satoshi Kondo; Tuan Thanh Ta; Hidenori Okuni; Kaori Watanabe; Masatoshi Hirono; Yoshinari Ojima; Katsuyuki Kimura; Sohichiroh Hosoda; Yutaka Ota; et al. (IEEE J. Solid State Circuits, 2018)

Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits. - Kentaro Yoshioka; Tomohiko Sugimoto; Naoya Waki; Sinnyoung Kim; Daisuke Kurose; Hirotomo Ishii; Masanori Furuta; Akihide Sai; Hiroki Ishikuro; Tetsuro Itakura (IEEE Trans. Very Large Scale Integr. Syst., 2019)