Power Variance Analysis breaks a masked ASIC implementation of AES. - Yang Li 001; Kazuo Sakiyama; Lejla Batina; Daisuke Nakatsu; Kazuo Ohta (DATE, 2010)

Combination of SW Countermeasure and CPU Modification on FPGA against Power Analysis. - Daisuke Nakatsu; Yang Li 001; Kazuo Sakiyama; Kazuo Ohta (WISA, 2010)

Clockwise Collision Analysis - Overlooked Side-Channel Leakage Inside Your Measurements. - Yang Li 001; Daisuke Nakatsu; Qi Li; Kazuo Ohta; Kazuo Sakiyama (IACR Cryptol. ePrint Arch., 2011)

Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest. - Christophe Clavier; Jean-Luc Danger; Guillaume Duc; M. Abdelaziz Elaabid; Benoît Gérard; Sylvain Guilley; Annelie Heuser; Michael Kasper; Yang Li 001; Victor Lomné; Daisuke Nakatsu; Kazuo Ohta; et al. (J. Cryptogr. Eng., 2014)