A Supporting System for Colored Knitting Design. - Daisuke Suzuki; Tsuyoshi Miyazaki 001; Koji Yamada; Tsuyoshi Nakamura; Hidenori Itoh (IEA/AIE, 2000)

A high-level synthesis method for simultaneous placement and scheduling considering data communication delay. - Kazuhito Ito; Daisuke Suzuki (APCCAS (1), 2002)

Two-dimensional mapping of impedance magnetocardiograms. - Akihiko Kandori; Tsuyoshi Miyashita; Daisuke Suzuki; Koichi Yokosawa; Keiji Tsukada (IEEE Trans. Biomed. Eng., 2002)

Random Switching Logic: A Countermeasure against DPA based on Transition Probability. - Daisuke Suzuki; Minoru Saeki; Tetsuya Ichikawa (IACR Cryptol. ePrint Arch., 2004)

DPA Leakage Models for CMOS Logic Circuits. - Daisuke Suzuki; Minoru Saeki; Tetsuya Ichikawa (CHES, 2005)

Word Vectors and Two Kinds of Similarity. - Akira Utsumi; Daisuke Suzuki (ACL, 2006)

Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style. - Daisuke Suzuki; Minoru Saeki (CHES, 2006)

How to Maximize the Potential of FPGA Resources for Modular Exponentiation. - Daisuke Suzuki (CHES, 2007)

Pulse-Width Modulation with Current Uniformization for TFT-OLEDs. - Mutsumi Kimura; Shigeki Sawamura; Masakazu Kato; Yuji Hara; Daisuke Suzuki; Hiroyuki Hara; Satoshi Inoue (IEICE Trans. Electron., 2007)

Leakage Analysis of DPA Countermeasures at the Logic Level. - Minoru Saeki; Daisuke Suzuki; Tetsuya Ichikawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level. - Daisuke Suzuki; Minoru Saeki; Tetsuya Ichikawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

High-Speed Search System for PGP Passphrases. - Koichi Shimizu; Daisuke Suzuki; Toyohiro Tsurumaru (CANS, 2008)

Security Evaluations of MRSL and DRSL Considering Signal Delays. - Minoru Saeki; Daisuke Suzuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style. - Daisuke Suzuki; Minoru Saeki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques. - Minoru Saeki; Daisuke Suzuki; Koichi Shimizu; Akashi Satoh (CHES, 2009)

Complementary logics vs masked logics: Which countermeasure is a better selection? - Tsutomu Matsumoto; Hidenobu Mimura; Daisuke Suzuki (ECCTD, 2009)

A Study of Auditory Warning Signals for the Design Guidelines of Man-Machine Interfaces. - Mie Nakatani; Daisuke Suzuki; Nobuchika Sakata; Shogo Nishida (HCI (9), 2009)

Olfaction Presentation System Using Odor Scanner and Odor-Emitting Apparatus Coupled with Chemical Capsules of Alginic Acid Polymer. - Minoru Sakairi; Ayako Nishimura; Daisuke Suzuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes. - Daisuke Suzuki; Koichi Shimizu (CHES, 2010)

Simultaneous detection of breath and alcohol using breath-alcohol sensor for prevention of drunk driving. - Minoru Sakairi; Daisuke Suzuki; Ayako Nishimura; Yukiko Ichige; Masashi Kiguchi (IEICE Electron. Express, 2010)

Increasing the Strength of Odors Produced by an Odor-Emitting Technology Using Odor Capsules. - Ayako Nishimura; Minoru Sakairi; Daisuke Suzuki (IEICE Trans. Inf. Syst., 2010)

High-Speed Passphrase Search System for PGP. - Koichi Shimizu; Daisuke Suzuki; Toyohiro Tsurumaru (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A Design Methodology for a DPA-Resistant Circuit with RSL Techniques. - Daisuke Suzuki; Minoru Saeki; Koichi Shimizu; Akashi Satoh; Tsutomu Matsumoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Phototactic and Chemotactic Signal Transduction by Transmembrane Receptors and Transducers in Microorganisms. - Daisuke Suzuki; Hiroki Irieda; Michio Homma; Ikuro Kawagishi; Yuki Sudo (Sensors, 2010)

How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation. - Daisuke Suzuki; Tsutomu Matsumoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

How to Decide Selection Functions for Power Analysis: From the Viewpoint of Hardware Architecture of Block Ciphers. - Daisuke Suzuki; Minoru Saeki; Koichi Shimizu; Tsutomu Matsumoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Circuit Simulation for Fault Sensitivity Analysis and Its Application to Cryptographic LSI. - Takeshi Sugawara 001; Daisuke Suzuki; Toshihiro Katashita (FDTC, 2012)

Dimensions of people's attitudes toward robots. - Daisuke Suzuki; Hiroyuki Umemuro (HRI, 2012)

Building Blocks to Use in Innovative Non-volatile FPGA Architecture Based on MTJs. - Luca Montesi; Zeljko Zilic; Takahiro Hanyu; Daisuke Suzuki (ISVLSI, 2012)

Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA. - Daisuke Suzuki; Masanori Natsui; Takahiro Hanyu (MWSCAS, 2012)

Glitch PUF: Extracting Information from Usually Unwanted Glitches. - Koichi Shimizu; Daisuke Suzuki; Tomomi Kasuya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. - Masanori Natsui; Daisuke Suzuki; Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Ayuka Morioka; Tadahiko Sugibayashi; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; et al. (ISSCC, 2013)

A visibility improvement technique for fog images suitable for real-time application. - Yoshitaka Toyoda; Daisuke Suzuki; Koichi Yamashita; Takashi Ito; Narihiro Matoba; Tetsuya Kuno; Hiroaki Sugiura 001 (Real-Time Image and Video Processing, 2013)

Cross-regional comparative study of dimensions of people's attitudes toward robots. - Akihito Fujita; Daisuke Suzuki; Hiroyuki Umemuro (RO-MAN, 2013)

Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. - Daisuke Suzuki; Masanori Natsui; Akira Mochizuki; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Hideo Sato; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (IEICE Electron. Express, 2013)

Metastable Ordered Phase Formation in CoPt and Co3Pt Alloy Thin Films Epitaxially Grown on Single-Crystal Substrates. - Mitsuru Ohtake; Daisuke Suzuki; Fumiyoshi Kirino; Masaaki Futamoto (IEICE Trans. Electron., 2013)

Using Pulse Laser Processing to Shape Cutting Edge of PcBN Tool for High-Precision Turning of Hardened Steel. - Daisuke Suzuki; Fumihiro Itoigawa; Keiichi Kawata; Takashi Nakamura (Int. J. Autom. Technol., 2013)

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. - Daisuke Suzuki; Noboru Sakimura; Masanori Natsui; Akira Mochizuki; Tadahiko Sugibayashi; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (IEICE Electron. Express, 2014)

Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication. - Koichi Shimizu; Daisuke Suzuki; Toyohiro Tsurumaru; Takeshi Sugawara 001; Mitsuru Shiozaki; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

On measurable side-channel leaks inside ASIC design primitives. - Takeshi Sugawara 001; Daisuke Suzuki; Minoru Saeki; Mitsuru Shiozaki; Takeshi Fujino (J. Cryptogr. Eng., 2014)

Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. - Takahiro Hanyu; Daisuke Suzuki; Naoya Onizawa; Shoun Matsunaga; Masanori Natsui; Akira Mochizuki (DATE, 2015)

PUF as a sensor. - Koichi Shimizu; Takeshi Sugawara 001; Daisuke Suzuki (GCCE, 2015)

Design of an MTJ-based nonvolatile lookup table circuit using an energy-efficient single-ended logic-in-memory structure. - Daisuke Suzuki; Takahiro Hanyu (MWSCAS, 2015)

Development of the Multi-dimensional Robot Attitude Scale: Constructs of People's Attitudes Towards Domestic Robots. - Takumi Ninomiya; Akihito Fujita; Daisuke Suzuki; Hiroyuki Umemuro (ICSR, 2015)

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. - Daisuke Suzuki; Masanori Natsui; Akira Mochizuki; Sadahiko Miura; Hiroaki Honjo; Hideo Sato; Shunsuke Fukami; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (VLSIC, 2015)

Two Operands of Multipliers in Side-Channel Attack. - Takeshi Sugawara 001; Daisuke Suzuki; Minoru Saeki (IACR Cryptol. ePrint Arch., 2015)

Faster Enumeration of All Maximal Cliques in Unit Disk Graphs Using Geometric Structure. - Taisuke Izumi; Daisuke Suzuki (IEICE Trans. Inf. Syst., 2015)

Reversing stealthy dopant-level circuits. - Takeshi Sugawara 001; Daisuke Suzuki; Ryoichi Fujii; Shigeaki Tawa; Ryohei Hori; Mitsuru Shiozaki; Takeshi Fujino (J. Cryptogr. Eng., 2015)

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. - Masanori Natsui; Daisuke Suzuki; Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Ayuka Morioka; Tadahiko Sugibayashi; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; et al. (IEEE J. Solid State Circuits, 2015)

Light-Weight Single Image Super-Resolution via Pattern-wise Regression Function. - Kohei Kurihara; Yoshitaka Toyoda; Shotaro Moriya; Daisuke Suzuki; Takeo Fujita; Narihiro Matoba; Jay E. Thorton; Fatih Porikli (Digital Photography and Mobile Imaging, 2016)

A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure. - Daisuke Suzuki; Takahiro Hanyu (FPL, 2016)

Zero-cross switching control of halogen lamp heater with delta-sigma modulator. - Daisuke Suzuki; Akihiko Yoneya (IECON, 2016)

Asymmetric Leakage from Multiplier and Collision-Based Single-Shot Side-Channel Attack. - Takeshi Sugawara 001; Daisuke Suzuki; Minoru Saeki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. - Takahiro Hanyu; Tetsuo Endoh; Daisuke Suzuki; Hiroki Koike; Yitao Ma; Naoya Onizawa; Masanori Natsui; Shoji Ikeda; Hideo Ohno (Proc. IEEE, 2016)

Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor. - Takahiro Hanyu; Daisuke Suzuki; Naoya Onizawa; Masanori Natsui (DATE, 2017)

Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme. - Daisuke Suzuki; Takahiro Hanyu (IEICE Trans. Inf. Syst., 2017)

Sensor CON-Fusion: Defeating Kalman Filter in Signal Injection Attack. - Shoei Nashimoto; Daisuke Suzuki; Takeshi Sugawara 001; Kazuo Sakiyama (AsiaCCS, 2018)

Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only). - Daisuke Suzuki; Takahiro Hanyu (FPGA, 2018)

Aggregation of Charged Microgels by Relatively Diamagnetic Assembly. - Hisae Suenaga; Haruka Minato; Daisuke Suzuki; Yoshitake Akiyama (MHS, 2018)

SAEB: A Lightweight Blockcipher-Based AEAD Mode of Operation. - Yusuke Naito 001; Mitsuru Matsui; Takeshi Sugawara 001; Daisuke Suzuki (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018)

Analysis of Driving Performance Data to Evaluate Brake Manipulation by Railway Drivers. - Daisuke Suzuki; Naoki Mizukami; Yutaka Kakizaki; Nobuyuki Tsuyuki (AHFE (13), 2019)

A Low-Cost Replica-Based Distance-Spoofing Attack on mmWave FMCW Radar. - Noriyuki Miura; Tatsuya Machida; Kohei Matsuda; Makoto Nagata; Shoei Nashimoto; Daisuke Suzuki (ASHES@CCS, 2019)

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (ISSCC, 2019)

A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (IEEE J. Solid State Circuits, 2019)

Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices. - Daisuke Suzuki; Takahiro Oka; Takahiro Hanyu (Microelectron. J., 2019)

Analysis of Driving Performance Data Considering the Characteristics of Railway Stations. - Daisuke Suzuki; Ayako Suzuki; Keiko Shimano; Kazuki Kiyota; Yutaka Kakizaki (AHFE (12), 2020)

Photoplethysmographic Subject Identification by Considering Feature Values Derived from Heartbeat and Respiration. - Shun Hinatsu; Daisuke Suzuki; Hiroki Ishizuka; Sei Ikeda; Osamu Oshiro (EMBC, 2020)

An Optimized Implementation of AES-GCM for FPGA Acceleration Using High-Level Synthesis. - Tsubasa Takaki; Yang Li 001; Kazuo Sakiyama; Shoei Nashimoto; Daisuke Suzuki; Takeshi Sugawara 001 (GCCE, 2020)

Design and Evaluation of a Synthesizable Standard-Cell-Based Nonvolatile FPGA. - Daisuke Suzuki; Takahiro Hanyu (ISMVL, 2020)

Bypassing Isolated Execution on RISC-V with Fault Injection. - Shoei Nashimoto; Daisuke Suzuki; Rei Ueno; Naofumi Homma (IACR Cryptol. ePrint Arch., 2020)

Towards Trained Model Confidentiality and Integrity Using Trusted Execution Environments. - Tsunato Nakai; Daisuke Suzuki; Takeshi Fujino (ACNS Workshops, 2021)

Attack on PPG Biometrics: Presentation Attack by Stealth Recording and Waveform Estimation. - Shun Hinatsu; Daisuke Suzuki; Hiroki Ishizuka; Sei Ikeda; Osamu Oshiro (EMBC, 2021)

A Memory-Access-Minimized BCNN Accelerator Using Nonvolatile FPGA with Only-Once- Write Shifting. - Daisuke Suzuki; Takahiro Oka; Takahiro Hanyu (MCSoC, 2021)

Evaluation Framework for Performance Limitation of Autonomous Systems Under Sensor Attack. - Koichi Shimizu; Daisuke Suzuki; Ryo Muramatsu; Hisashi Mori; Tomoyuki Nagatsuka; Tsutomu Matsumoto (SAFECOMP, 2021)

Adversarial Black-Box Attacks with Timing Side-Channel Leakage. - Tsunato Nakai; Daisuke Suzuki; Fumio Omatsu; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow. - Daisuke Suzuki; Takahiro Hanyu (IEICE Trans. Inf. Syst., 2021)

Low-cost distance-spoofing attack on FMCW radar and its feasibility study on countermeasure. - Shoei Nashimoto; Daisuke Suzuki; Noriyuki Miura; Tatsuya Machida; Kohei Matsuda; Makoto Nagata (J. Cryptogr. Eng., 2021)

Timing Black-Box Attacks: Crafting Adversarial Examples through Timing Leaks against DNNs on Embedded Devices. - Tsunato Nakai; Daisuke Suzuki; Takeshi Fujino (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021)

Towards Isolated AI Accelerators with OP-TEE on SoC-FPGAs. - Tsunato Nakai; Daisuke Suzuki; Takeshi Fujino (ACNS Workshops, 2022)

Construction of a Quality Estimation Dataset for Automatic Evaluation of Japanese Grammatical Error Correction. - Daisuke Suzuki; Yujin Takahashi; Ikumi Yamashita; Taichi Aida; Tosho Hirasawa; Michitaka Nakatsuji; Masato Mita; Mamoru Komachi (LREC, 2022)

A Spintronics-Based Nonvolatile FPGA and Its Application to Edge-AI Accelerator. - Daisuke Suzuki; Takahiro Hanyu (MCSoC, 2022)

Orbital Demonstration of Gossamer Structure Shape Estimation using Time-of-Flight Camera System. - Toshinori Kuwahara; Alperen Pala; Adrien Potier; Yoshihiko Shibuya; Yuji Sato; Shinya Fujita 002; Daisuke Suzuki; Tetsuya Kaneko (SII, 2022)

Orbital Maneuver Evaluation of Micro-satellite ALE-1 with a Separable Drag Sail. - Alperen Pala; Toshinori Kuwahara; Kohei Takeda; Yoshihiko Shibuya; Yuji Sato; Shinya Fujita 002; Daisuke Suzuki; Tetsuya Kaneko (SII, 2022)

Attitude Control System Design of 3U CubeSat with Electrodynamic Tether for Post Mission Disposal Demonstration. - Naoya Shiraishi; Yuji Sato; Yoshihiko Shibuya; Shinya Fujita 002; Toshinori Kuwahara; Daisuke Suzuki (SII, 2022)

Evaluation of PPG Feature Values Toward Biometric Authentication Against Presentation Attacks. - Shun Hinatsu; Daisuke Suzuki; Hiroki Ishizuka; Sei Ikeda; Osamu Oshiro (IEEE Access, 2022)

Bypassing Isolated Execution on RISC-V using Side-Channel-Assisted Fault-Injection and Its Countermeasure. - Shoei Nashimoto; Daisuke Suzuki; Rei Ueno; Naofumi Homma (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

Design of a Nonvolatile-Neural-Network-Accelerator-Embedded Edge-IoT Device and Its Hardware Emulation. - Ken Sato; Daisuke Suzuki (MCSoC, 2023)

An FPGA-based rapid-prototyping platform for spintronics-based edge-computing hardware. - Daisuke Suzuki; Akira Tamakoshi; Tomohiro Yoneda; Masanori Natsui; Yasuhiro Takako; Takahiro Hanyu (ISMVL, 2025)

Implementation of an MRAM-Based Edge AI Hardware with a Fine-Grained Power-Gating Technique. - Tomohiro Yoneda; Yasuhiro Takako; Akira Tamakoshi; Masanori Natsui; Daisuke Suzuki; Takahiro Hanyu (ISMVL, 2025)