A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264. - Dajiang Zhou; Peilin Liu (ISCAS, 2007)

An SDRAM controller optimized for high definition video coding application. - Jiayi Zhu 001; Peilin Liu; Dajiang Zhou (ISCAS, 2008)

A 136 cycles/MB, luma-chroma parallelized H.264/AVC deblocking filter for QFHD applications. - Jinjia Zhou; Dajiang Zhou; Hang Zhang; Yu Hong; Peilin Liu; Satoshi Goto (ICME, 2009)

Block-pipelining Cache for Motion Compensation in High Definition H.264/AVC Video Decoder. - Xianmin Chen; Peilin Liu; Jiayi Zhu 001; Dajiang Zhou; Satoshi Goto (ISCAS, 2009)

Prioritized Reference Decision for Efficient Motion Vector Coding. - Dajiang Zhou; Jinjia Zhou; Satoshi Goto (ISCAS, 2009)

An Efficient Motion Vector Coding Scheme Based on Prioritized Reference Decision. - Dajiang Zhou; Jinjia Zhou; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications. - Dajiang Zhou; Jinjia Zhou; Jiayi Zhu 001; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A constant rate bandwidth reduction architecture with adaptive compression mode decision for video decoding. - Liu Song; Dajiang Zhou; Xin Jin 002; Satoshi Goto (EUSIPCO, 2010)

An advanced hierarchical motion estimation scheme with lossless frame recompression for ultra high definition video coding. - Xuena Bao; Dajiang Zhou; Peilin Liu; Satoshi Goto (ICME, 2010)

A lossless frame recompression scheme for reducing DRAM power in video encoding. - Xuena Bao; Dajiang Zhou; Satoshi Goto (ISCAS, 2010)

An early stopping criterion for decoding LDPC codes in WiMAX and WiFi standards. - Zhixiang Chen 002; Xiongxin Zhao; Xiao Peng 002; Dajiang Zhou; Satoshi Goto (ISCAS, 2010)

An adaptive bandwidth reduction scheme for video coding. - Liu Song; Dajiang Zhou; Xin Jin 002; Satoshi Goto; Peilin Liu (ISCAS, 2010)

A Bandwidth Reduction Scheme and Its VLSI Implementation for H.264/AVC Motion Vector Decoding. - Jinjia Zhou; Dajiang Zhou; Gang He 002; Satoshi Goto (PCM (2), 2010)

Intra prediction architecture for H.264/AVC QFHD encoder. - Gang He 002; Dajiang Zhou; Jinjia Zhou; Satoshi Goto (PCS, 2010)

A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder. - Xianmin Chen; Peilin Liu; Dajiang Zhou; Jiayi Zhu 001; Xingguang Pan; Satoshi Goto (IEICE Trans. Electron., 2010)

A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications. - Jinjia Zhou; Dajiang Zhou; Xun He; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A High Parallelism LDPC Decoder with an Early Stopping Criterion for WiMax and WiFi Application. - Zhixiang Chen 002; Xiongxin Zhao; Xiao Peng 002; Dajiang Zhou; Satoshi Goto (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

High Profile Intra Prediction Architecture for UHD H.264 Decoder. - Xun He; Dajiang Zhou; Jinjia Zhou; Satoshi Goto (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS. - Xiao Peng 002; Zhixiang Chen 002; Xiongxin Zhao; Dajiang Zhou; Satoshi Goto (A-SSCC, 2011)

A 1 Gbin/s CABAC encoder for H.264/AVC. - Wei Fei; Dajiang Zhou; Satoshi Goto (EUSIPCO, 2011)

A 16-65 cycles/MB H.264/AVC motion compensation architecture for Quad-HD applications. - Jinjia Zhou; Dajiang Zhou; Gang He 002; Satoshi Goto (EUSIPCO, 2011)

A 98 GMACs/W 32-core vector processor in 65nm CMOS. - Xun He; Dajiang Zhou; Xin Jin 002; Satoshi Goto (ISLPED, 2011)

A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering. - Qian Xie; Qian He; Xiao Peng 002; Ying Cui; Zhixiang Chen 002; Dajiang Zhou; Satoshi Goto (SiPS, 2011)

Ultra low power QC-LDPC decoder with high parallelism. - Ying Cui; Xiao Peng 002; Zhixiang Chen 002; Xiongxin Zhao; Yichao Lu; Dajiang Zhou; Satoshi Goto (SoCC, 2011)

A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip. - Zhixiang Chen 002; Xiao Peng 002; Xiongxin Zhao; Leona Okamura; Dajiang Zhou; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS. - Xun He; Xin Jin 002; Minghui Wang; Dajiang Zhou; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder. - Gang He 002; Dajiang Zhou; Jinjia Zhou; Tianruo Zhang; Satoshi Goto (IEICE Trans. Electron., 2011)

Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder. - Jinjia Zhou; Dajiang Zhou; Gang He 002; Satoshi Goto (IEICE Trans. Electron., 2011)

A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip. - Dajiang Zhou; Jinjia Zhou; Xun He; Jiayi Zhu 001; Ji Kong; Peilin Liu; Satoshi Goto (IEEE J. Solid State Circuits, 2011)

A 1991 Mpixels/s intra prediction architecture for Super Hi-Vision H.264/AVC encoder. - Gang He 002; Dajiang Zhou; Jinjia Zhou; Satoshi Goto (EUSIPCO, 2012)

An optimized MC interpolation architecture for HEVC. - Zhengyan Guo; Dajiang Zhou; Satoshi Goto (ICASSP, 2012)

Interlaced asymmetric search range assignment for bidirectional motion estimation. - Jinjia Zhou; Dajiang Zhou; Satoshi Goto (ICIP, 2012)

A Low-Complexity HEVC Intra Prediction Algorithm Based on Level and Mode Filtering. - Heming Sun; Dajiang Zhou; Satoshi Goto (ICME, 2012)

A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications. - Dajiang Zhou; Jinjia Zhou; Jiayi Zhu 001; Peilin Liu; Satoshi Goto (ISSCC, 2012)

De-blocking Filter Design for HEVC and H.264/AVC. - Muchen Li; Jinjia Zhou; Dajiang Zhou; Xiao Peng 002; Satoshi Goto (PCM, 2012)

A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC. - Dajiang Zhou; Gang He 002; Wei Fei; Zhixiang Chen 002; Jinjia Zhou; Satoshi Goto (VLSIC, 2012)

A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX. - Xiongxin Zhao; Xiao Peng 002; Zhixiang Chen 002; Dajiang Zhou; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

DVB-T2 LDPC Decoder with Perfect Conflict Resolution. - Xiongxin Zhao; Zhixiang Chen 002; Xiao Peng 002; Dajiang Zhou; Satoshi Goto (IPSJ Trans. Syst. LSI Des. Methodol., 2012)

An Advanced Hierarchical Motion Estimation Scheme With Lossless Frame Recompression and Early-Level Termination for Beyond High-Definition Video Coding. - Xuena Bao; Dajiang Zhou; Peilin Liu; Satoshi Goto (IEEE Trans. Multim., 2012)

Transform-based fast mode and depth decision algorithm for HEVC intra prediction. - Gang He 002; Dajiang Zhou; Satoshi Goto (ASICON, 2013)

A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS. - Zhixiang Chen 002; Xiao Peng 002; Xiongxin Zhao; Leona Okamura; Dajiang Zhou; Satoshi Goto (ASP-DAC, 2013)

A 24.5-53.6pJ/pixel 4320p 60fps H.264/AVC intra-frame video encoder chip in 65nm CMOS. - Dajiang Zhou; Gang He 002; Wei Fei; Zhixiang Chen 002; Jinjia Zhou; Satoshi Goto (ASP-DAC, 2013)

Lossless embedded compression using multi-mode DPCM & averaging prediction for HEVC-like video codec. - Li Guo 006; Dajiang Zhou; Satoshi Goto (EUSIPCO, 2013)

A high-performance CABAC encoder architecture for HEVC and H.264/AVC. - Jinjia Zhou; Dajiang Zhou; Wei Fei; Satoshi Goto (ICIP, 2013)

A combined SAO and de-blocking filter architecture for HEVC video decoder. - Jiayi Zhu 001; Dajiang Zhou; Gang He 002; Satoshi Goto (ICIP, 2013)

An FPGA-based 4K UHDTV H.264/AVC video decoder. - Yue Pan; Dajiang Zhou; Satoshi Goto (ICME Workshops, 2013)

High-parallel performance-aware LDPC decoder IP core design for WiMAX. - Xiongxin Zhao; Zhixiang Chen 002; Xiao Peng 002; Dajiang Zhou; Satoshi Goto (MWSCAS, 2013)

A Dual-Mode Deblocking Filter Design for HEVC and H.264/AVC. - Muchen Li; Jinjia Zhou; Dajiang Zhou; Xiao Peng 002; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS. - Xiongxin Zhao; Zhixiang Chen 002; Xiao Peng 002; Dajiang Zhou; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder. - Jiayi Zhu 001; Dajiang Zhou; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Live demonstration: FPGA based 3840×2160 video decoding and displaying system. - Haoming Zhang; Dajiang Zhou; Satoshi Goto (APCCAS, 2014)

OpenCL based high-quality HEVC motion estimation on GPU. - Fan Wang; Dajiang Zhou; Satoshi Goto (ICIP, 2014)

A 610 Mbin/s CABAC decoder for H.265/HEVC level 6.1 applications. - Yijin Zhao; Jinjia Zhou; Dajiang Zhou; Satoshi Goto (ICIP, 2014)

Reducing power consumption of HEVC codec with lossless reference frame recompression. - Dajiang Zhou; Li Guo 006; Jinjia Zhou; Satoshi Goto (ICIP, 2014)

VLSI architecture of HEVC intra prediction for 8K UHDTV applications. - Jian-Bin Zhou; Dajiang Zhou; Heming Sun; Satoshi Goto (ICIP, 2014)

Fast SAO estimation algorithm and its VLSI architecture. - Jiayi Zhu 001; Dajiang Zhou; Shinji Kimura; Satoshi Goto (ICIP, 2014)

Motion compensation architecture for 8K UHDTV HEVC decoder. - Shihao Wang; Dajiang Zhou; Satoshi Goto (ICME, 2014)

Low-Complexity Rate-Distortion Optimization Algorithms for HEVC Intra Prediction. - Zhe Sheng; Dajiang Zhou; Heming Sun; Satoshi Goto (MMM (1), 2014)

Unified VLSI Architecture of Motion Vector and Boundary Strength Parameter Decoder for 8K UHDTV HEVC Decoder. - Shihao Wang; Dajiang Zhou; Jian-Bin Zhou; Takeshi Yoshimura; Satoshi Goto (PCM, 2014)

An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder. - Heming Sun; Dajiang Zhou; Jiayi Zhu 001; Shinji Kimura; Satoshi Goto (VCIP, 2014)

A low power 720p motion estimation processor with 3D stacked memory. - Shuping Zhang; Jinjia Zhou; Dajiang Zhou; Satoshi Goto (VLSI-SoC, 2014)

Fast Prediction Unit Selection and Mode Selection for HEVC Intra Prediction. - Heming Sun; Dajiang Zhou; Peilin Liu; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A Low-Cost VLSI Architecture of Multiple-Size IDCT for H.265/HEVC. - Heming Sun; Dajiang Zhou; Peilin Liu; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Fast SAO Estimation Algorithm and Its Implementation for 8K×4K @ 120 FPS HEVC Encoding. - Jiayi Zhu 001; Dajiang Zhou; Shinji Kimura; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A 1.59 Gpixel/s Motion Estimation Processor With -211 to +211 Search Range for UHDTV Video Encoder. - Dajiang Zhou; Jinjia Zhou; Gang He 002; Satoshi Goto (IEEE J. Solid State Circuits, 2014)

Alternating asymmetric search range assignment for bidirectional motion estimation in H.265/HEVC and H.264/AVC. - Jinjia Zhou; Dajiang Zhou; Satoshi Goto (J. Vis. Commun. Image Represent., 2014)

A New Reference Frame Recompression Algorithm and Its VLSI Architecture for UHDTV Video Codec. - Li Guo 006; Dajiang Zhou; Satoshi Goto (IEEE Trans. Multim., 2014)

High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications. - Gang He 002; Dajiang Zhou; Wei Fei; Zhixiang Chen 002; Jinjia Zhou; Satoshi Goto (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A full layer parallel QC-LDPC decoder for WiMAX and Wi-Fi. - Wenchao Zhang; Song Chen 001; Xuefei Bai; Dajiang Zhou (ASICON, 2015)

Hardware-oriented rate-distortion optimization algorithm for HEVC intra-frame encoder. - Landan Hu; Heming Sun; Dajiang Zhou; Shinji Kimura (ICME Workshops, 2015)

A fixed-complexity HEVC inter mode filtering algorithm based on distribution of IME-FME cost ratio. - Jinjia Zhou; Yizhou Zou; Dajiang Zhou; Satoshi Goto (ISCAS, 2015)

An independent bandwidth reduction device for HEVC VLSI video system. - Jiayi Zhu 001; Li Guo 006; Dajiang Zhou; Shinji Kimura; Satoshi Goto (ISCAS, 2015)

Merge mode based fast inter prediction for HEVC. - Zhengxue Cheng; Heming Sun; Dajiang Zhou; Shinji Kimura (VCIP, 2015)

Unified Parameter Decoder Architecture for H.265/HEVC Motion Vector and Boundary Strength Decoding. - Shihao Wang; Dajiang Zhou; Jian-Bin Zhou; Takeshi Yoshimura; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Low-Power Motion Estimation Processor with 3D Stacked Memory. - Shuping Zhang; Jinjia Zhou; Dajiang Zhou; Shinji Kimura; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

High Performance VLSI Architecture of H.265/HEVC Intra Prediction for 8K UHDTV Video Decoder. - Jian-Bin Zhou; Dajiang Zhou; Shihao Wang; Takeshi Yoshimura; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Ultra-High-Throughput VLSI Architecture of H.265/HEVC CABAC Encoder for UHDTV Applications. - Dajiang Zhou; Jinjia Zhou; Wei Fei; Satoshi Goto (IEEE Trans. Circuits Syst. Video Technol., 2015)

High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding. - Gang He 002; Dajiang Zhou; Yunsong Li 001; Zhixiang Chen 002; Tianruo Zhang; Satoshi Goto (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications. - Jinjia Zhou; Dajiang Zhou; Jiayi Zhu 001; Satoshi Goto (IEEE Trans. Very Large Scale Integr. Syst., 2015)

CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks. - Xushen Han; Dajiang Zhou; Shihao Wang; Shinji Kimura (ICCD, 2016)

Frame-level quality and memory traffic allocation for lossy embedded compression in video codec systems. - Li Guo 006; Dajiang Zhou; Shinji Kimura; Satoshi Goto (ICME Workshops, 2016)

14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications. - Dajiang Zhou; Shihao Wang; Heming Sun; Jian-Bin Zhou; Jiayi Zhu 001; Yijin Zhao; Jinjia Zhou; Shuping Zhang; Shinji Kimura; Takeshi Yoshimura; Satoshi Goto (ISSCC, 2016)

HyDMA: low-latency inter-core DMA based on a hybrid packet-circuit switching network-on-chip. - Zhenqi Wei; Peilin Liu; Rongdi Sun; Zunquan Zhou; Ke Jin; Dajiang Zhou (IEICE Electron. Express, 2016)

A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform. - Heming Sun; Dajiang Zhou; Shuping Zhang; Shinji Kimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networks. - Shihao Wang; Dajiang Zhou; Xushen Han; Takeshi Yoshimura (DATE, 2017)

Measurement-domain intra prediction framework for compressively sensed images. - Jian-Bin Zhou; Dajiang Zhou; Li Guo 006; Takeshi Yoshimura; Satoshi Goto (ISCAS, 2017)

Approximate-DCT-derived measurement matrices for compressed sensing. - Jian-Bin Zhou; Dajiang Zhou; Takeshi Yoshimura; Satoshi Goto (ISCAS, 2017)

100x Evolution of Video Codec Chips. - Jinjia Zhou; Dajiang Zhou; Satoshi Goto (ISPD, 2017)

Accelerating HEVC Inter Prediction with Improved Merge Mode Handling. - Zhengxue Cheng; Heming Sun; Dajiang Zhou; Shinji Kimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Distortion Control and Optimization for Lossy Embedded Compression in Video Codec System. - Li Guo 006; Dajiang Zhou; Shinji Kimura; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor. - Shuping Zhang; Jinjia Zhou; Dajiang Zhou; Shinji Kimura; Satoshi Goto (IEICE Trans. Electron., 2017)

Framework and VLSI Architecture of Measurement-Domain Intra Prediction for Compressively Sensed Visual Contents. - Jian-Bin Zhou; Dajiang Zhou; Li Guo 006; Takeshi Yoshimura; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design. - Dajiang Zhou; Shihao Wang; Heming Sun; Jian-Bin Zhou; Jiayi Zhu 001; Yijin Zhao; Jinjia Zhou; Shuping Zhang; Shinji Kimura; Takeshi Yoshimura; Satoshi Goto (IEEE J. Solid State Circuits, 2017)

VLSI Implementation of HEVC Motion Compensation With Distance Biased Direct Cache Mapping for 8K UHDTV Applications. - Shihao Wang; Dajiang Zhou; Jian-Bin Zhou; Takeshi Yoshimura; Satoshi Goto (IEEE Trans. Circuits Syst. Video Technol., 2017)

Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC. - Heming Sun; Dajiang Zhou; Landan Hu; Shinji Kimura; Satoshi Goto (IEEE Trans. Multim., 2017)

A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding. - Jian-Bin Zhou; Dajiang Zhou; Shihao Wang; Shuping Zhang; Takeshi Yoshimura; Satoshi Goto (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA. - Zhifeng Zhang 003; Dajiang Zhou; Shihao Wang; Shinji Kimura (ASP-DAC, 2018)

Embedded Frame Compression for Energy-Efficient Computer Vision Systems. - Li Guo 006; Dajiang Zhou; Jinjia Zhou; Shinji Kimura (ISCAS, 2018)

Sparseness Ratio Allocation and Neuron Re-pruning for Neural Networks Compression. - Li Guo 006; Dajiang Zhou; Jinjia Zhou; Shinji Kimura (ISCAS, 2018)

Lossy Compression for Embedded Computer Vision Systems. - Li Guo 006; Dajiang Zhou; Jinjia Zhou; Shinji Kimura; Satoshi Goto (IEEE Access, 2018)

Approximate-DCT-Derived Measurement Matrices with Row-Operation-Based Measurement Compression and its VLSI Architecture for Compressed Sensing. - Jian-Bin Zhou; Dajiang Zhou; Takeshi Yoshimura; Satoshi Goto (IEICE Trans. Electron., 2018)

A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC. - Jinjia Zhou; Dajiang Zhou; Shuping Zhang; Shinji Kimura; Satoshi Goto (IEEE Trans. Circuits Syst. Video Technol., 2018)

Perceptual Image Compression Using Relativistic Average Least Squares GANs. - Zhengxue Cheng; Ting Fu; Jiapeng Hu; Li Guo 006; Shihao Wang; Xiongxin Zhao; Dajiang Zhou; Yang Song (CVPR Workshops, 2021)

Efficient Deep Models for Real-Time 4K Image Super-Resolution. NTIRE 2023 Benchmark and Report. - Marcos V. Conde; Eduard Zamfir; Radu Timofte; Daniel Motilla; Cen Liu; Zexin Zhang; Yunbo Peng; Yue Lin 002; Jiaming Guo; Xueyi Zou; Yuyi Chen; Yi Liu; et al. (CVPR Workshops, 2023)

A High Resolution SAR Imaging Method for Moving Target Based on Range Doppler and Particle Swarm Optimization Algorithm. - Dajiang Zhou; Hanqing Zhu; Yulin Huang 001; Yongchao Zhang 001; Jianyu Yang 001; Qingying Yi (IGARSS, 2023)

Moving Target Detection Method for Passive Radar Using LEO Communication Satellite Constellation. - Hanqing Zhu; Dajiang Zhou; Zhongyu Li 001; Hongyang An; Chuan Huang; Yun Zhou; Jianyu Yang 001 (IGARSS, 2023)

QuantNAS: Quantization-aware Neural Architecture Search For Efficient Deployment On Mobile Device. - Tianxiao Gao; Li Guo 006; Shanwei Zhao; Peihan Xu; Yukun Yang; Xionghao Liu; Shihao Wang; Shiai Zhu; Dajiang Zhou (CVPR Workshops, 2024)

Beyond Feature Mapping GAP: Integrating Real HDRTV Priors for Superior SDRTV-to-HDRTV Conversion. - Kepeng Xu; Li Xu 008; Gang He 002; Zhiqiang Zhang; Wenxin Yu 001; Shihao Wang; Dajiang Zhou; Yunsong Li 001 (CoRR, 2024)

Multi-Frame Deformable Look-Up Table for Compressed Video Quality Enhancement. - Gang He 002; Guancheng Quan; Chang Wu 001; Shihao Wang; Dajiang Zhou; Yunsong Li 001 (AAAI, 2025)

L3TC: Leveraging RWKV for Learned Lossless Low-Complexity Text Compression. - Junxuan Zhang; Zhengxue Cheng; Yan Zhao; Shihao Wang; Dajiang Zhou; Guo Lu; Li Song (AAAI, 2025)

RivuletMLP: An MLP-based Architecture for Efficient Compressed Video Quality Enhancement. - Gang He 002; Weiran Wang; Guancheng Quan; Shihao Wang; Dajiang Zhou; Yunsong Li 001 (CVPR, 2025)

PQNAS: Mixed-precision Quantization-aware Neural Architecture Search with Pseudo Quantizer. - Tianxiao Gao; Li Guo 006; Shihao Wang; Shiai Zhu; Dajiang Zhou (ICASSP, 2025)