Trading speed for low power by choice of supply and threshold voltages. - Dake Liu; Christer Svensson (IEEE J. Solid State Circuits, 1993)

Power consumption estimation in CMOS VLSI chips. - Dake Liu; Christer Svensson (IEEE J. Solid State Circuits, 1994)

VLSI implementation of CRC-32 for 10 Gigabit Ethernet. - Tomas Henriksson; Henrik Eriksson; Ulf Nordqvist; Per Larsson-Edefors; Dake Liu (ICECS, 2001)

Embedded Protocol Processor for Fast and Efficient Packet Reception. - Tomas Henriksson; Ulf Nordqvist; Dake Liu (ICCD, 2002)

Implementation of fast CRC calculation. - Tomas Henriksson; Dake Liu (ASP-DAC, 2003)

A general DSP processor at the cost of 23K gates and 1/2 a man-year design time. - Eric Tell; Mikael Olausson; Dake Liu (ICASSP (2), 2003)

Power optimized packet buffering in a protocol processor. - Ulf Nordqvist; Dake Liu (ICECS, 2003)

SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems. - Daniel Wiklund; Dake Liu (IPDPS, 2003)

A converged hardware solution for FFT, DCT and Walsh transform. - Eric Tell; Olle Seger; Dake Liu (ISSPA (1), 2003)

Reduced floating point for MPEG1/2 layer III decoding. - Mikael Olausson; Andreas Ehliar; Johan Eilert; Dake Liu (ICASSP (5), 2004)

Design of a guaranteed throughput router for on-chip networks. - Sumant Sathe; Daniel Wiklund; Dake Liu (SoC, 2004)

Bit Memory Instructions for a General CPU. - Mikael Olausson; Anders Edman; Dake Liu (IWSOC, 2004)

Network on Chip Simulations for Benchmarking. - Daniel Wiklund; Sumant Sathe; Dake Liu (IWSOC, 2004)

Using low precision floating point numbers to reduce memory cost for MP3 decoding. - Johan Eilert; Andreas Ehliar; Dake Liu (MMSP, 2004)

Network processors for access network (NP4AN): trends and challenges. - Xiaoning Nie; Ulf Nordqvist; Lajos Gazsi; Dake Liu (SoCC, 2004)

Flexible route lookup using range search. - Andreas Ehliar; Dake Liu (Communications and Computer Networks, 2005)

A programmable SIMD-based multi-standard Rake receiver architecture. - Anders Nilsson 001; Eric Tell; Dake Liu (EUSIPCO, 2005)

A Low Area and Low Power Programmable Baseband Processor Architecture. - Eric Tell; Anders Nilsson 001; Dake Liu (IWSOC, 2005)

Design Mapping, and Simulations of a 3G WCDMA/FDD Basestation Using Network on Chip. - Daniel Wiklund; Dake Liu (IWSOC, 2005)

A Single Issue DSP based Multi-standard Media Processor for Mobile Platforms. - Di Wu 003; Tiejun Hu; Dake Liu (ARCS Workshops, 2006)

Accelerating CABAC encoding for multi-standard media with configurability. - Oskar Flordal; Di Wu 003; Dake Liu (IPDPS, 2006)

MIPS cost estimation for OFDM-VBLAST systems. - Haiyan Jiao; Anders Nilsson 001; Eric Tell; Dake Liu (WCNC, 2006)

An fpga based open source network-on-chip architecture. - Andreas Ehliar; Dake Liu (FPL, 2007)

Efficient Complex Matrix Inversion for MIMO Software Defined Radio. - Johan Eilert; Di Wu 003; Dake Liu (ISCAS, 2007)

Fast Complex Valued Matrix Inversion for Multi-User STBC-MIMO Decoding. - Di Wu 003; Johan Eilert; Dake Liu; Dandan Wang 001; Naofal Al-Dhahir; Hlaing Minn (ISVLSI, 2007)

Lattice-Reduction Aided Multi-User STBC Decoding with Resource Constraints. - Di Wu 003; Johan Eilert; Dake Liu (PIMRC, 2007)

Area Efficient Fully Programmable Baseband Processors. - Anders Nilsson 001; Dake Liu (SAMOS, 2007)

A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA. - Andreas Ehliar; Per Karlström; Dake Liu (FPL, 2008)

Implementation of a programmable linear MMSE detector for MIMO-OFDM. - Johan Eilert; Di Wu 003; Dake Liu (ICASSP, 2008)

An 11mm2 70mW Fully-Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12μm CMOS. - Anders Nilsson 001; Eric Tell; Dake Liu (ISSCC, 2008)

Dual standard re-configurable hardware interleaver for turbo decoding. - Rizwan Asghar; Dake Liu (ISWPC, 2008)

Cost Analysis of Channel Estimation in MIMO-OFDM for Software Defined Radio. - Qi Wang; Di Wu 003; Johan Eilert; Dake Liu (WCNC, 2008)

High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4. - Per Karlström; Andreas Ehliar; Dake Liu (IET Comput. Digit. Tech., 2008)

Large Matrix Multiplication on a Novel Heterogeneous Parallel DSP Architecture. - Joar Sohl; Jian Wang 035; Dake Liu (APPT, 2009)

Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution. - Rizwan Asghar; Di Wu 003; Johan Eilert; Dake Liu (DSD, 2009)

Evaluation of MIMO symbol detectors for 3GPP LTE terminals. - Di Wu 003; Johan Eilert; Dake Liu (EUSIPCO, 2009)

An ASIC perspective on FPGA optimizations. - Andreas Ehliar; Dake Liu (FPL, 2009)

Low Complexity Hardware Interleaver for MIMO-OFDM based Wireless LAN. - Rizwan Asghar; Dake Liu (ISCAS, 2009)

System architecture for 3GPP LTE modem using a programmable baseband processor. - Di Wu 003; Johan Eilert; Dake Liu; Anders Nilsson 001; Eric Tell; Eric Alfredsson (SoC, 2009)

NoGAP: A Micro Architecture Construction Framework. - Per Karlström; Dake Liu (SAMOS, 2009)

Implementation Aspects of Fixed-Complexity Soft-Output MIMO Detection. - Di Wu 003; Erik G. Larsson; Dake Liu (VTC Spring, 2009)

Bridging dream and reality: Programmable baseband processors for software-defined radio. - Dake Liu; Anders Nilsson 001; Eric Tell; Di Wu 003; Johan Eilert (IEEE Commun. Mag., 2009)

An 11 mm2, 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12µm CMOS. - Anders Nilsson 001; Eric Tell; Dake Liu (IEEE J. Solid State Circuits, 2009)

Application Specific Instruction Set DSP Processors. - Dake Liu (Handbook of Signal Processing Systems, 2010)

NoGapCL: A flexible common language for processor hardware description. - Wenbiao Zhou; Per Karlström; Dake Liu (DDECS, 2010)

Software Programmable Data Allocation in Multi-bank Memory of SIMD Processors. - Jian Wang 035; Joar Sohl; Olof Kraigher; Dake Liu (DSD, 2010)

Implementation of a Floating Point Adder and Subtracter in NoGAP, A Comparative Case Study. - Per Karlström; Wenbiao Zhou; Dake Liu (EUC, 2010)

Architectural Support for Reducing Parallel Processing Overhead in an Embedded Multiprocessor. - Jian Wang 035; Joar Sohl; Dake Liu (EUC, 2010)

Operation Classification for Control Path Synthetization with NoGAP. - Per Karlström; Wenbiao Zhou; Dake Liu (ITNG, 2010)

Automatic port and bus sizing in NoGap. - Per Karlström; Wenbiao Zhou; Dake Liu (ICSAMOS, 2010)

VLSI implementation of A multi-standard MIMO symbol detector for 3GPP LTE and WiMAX. - Di Wu 003; Johan Eilert; Rizwan Asghar; Dake Liu; Magic Ge (WTS, 2010)

VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless. - Di Wu 003; Johan Eilert; Rizwan Asghar; Dake Liu (EURASIP J. Wirel. Commun. Netw., 2010)

Parallel Programming and Its Architectures Based on Data Access Separated Algorithm Kernels. - Dake Liu; Joar Sohl; Jian Wang 035 (Int. J. Embed. Real Time Commun. Syst., 2010)

System Architecture for 3GPP-LTE Modem using a Programmable Baseband Processor. - Di Wu 003; Johan Eilert; Rizwan Asghar; Dake Liu; Anders Nilsson 001; Eric Tell; Eric Alfredsson (Int. J. Embed. Real Time Commun. Syst., 2010)

Multimode Flex-Interleaver Core for Baseband Processor Platform. - Rizwan Asghar; Dake Liu (J. Comput. Networks Commun., 2010)

Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding. - Rizwan Asghar; Di Wu 003; Johan Eilert; Dake Liu (J. Signal Process. Syst., 2010)

ePUMA embedded parallel DSP processor with Unique Memory Access. - Dake Liu; Andreas Karlsson; Joar Sohl; Jian Wang 035; Magnus Pettersson; Wenbiao Zhou (ICICS, 2011)

A multi-level arbitration and topology free streaming network for chip multiprocessor. - Jian Wang 035; Andreas Karlsson; Joar Sohl; Magnus Pettersson; Dake Liu (ASICON, 2011)

Case Study of Efficient Parallel Memory Access Programming for the Embedded Heterogeneous Multicore DSP Architecture ePUMA. - Erik Hansson; Joar Sohl; Christoph W. Kessler; Dake Liu (CISIS, 2011)

Implementation Aspects of Channel Estimation for 3GPP LTE Terminals. - Michal Simko; Di Wu 003; Christian Mehlführer; Johan Eilert; Dake Liu (EW, 2011)

An Efficient Streaming Star Network for Multi-core Parallel DSP Processor. - Jian Wang 035; Joar Sohl; Andreas Karlsson; Dake Liu (ICNC, 2011)

Implementation of a High-Speed MIMO Soft-Output Symbol Detector for Software Defined Radio. - Di Wu 003; Johan Eilert; Dake Liu (J. Signal Process. Syst., 2011)

Automatic Synthesizable HDL Generator for NoGAP. - Wenbiao Zhou; Per Karlström; Dake Liu (ACIS-ICIS, 2012)

Convolutional Decoding on Deep-pipelined SIMD Processor with Flexible Parallel Memory. - Jian Wang 035; Andreas Karlsson; Joar Sohl; Dake Liu (DSD, 2012)

Automatic Permutation for Arbitrary Static Access Patterns. - Joar Sohl; Jian Wang 035; Andreas Karlsson; Dake Liu (ISPA, 2012)

Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support. - Rizwan Asghar; Di Wu 003; Ali Saeed; Yulin Huang; Dake Liu (J. Signal Process. Syst., 2012)

ePUMA: A unique memory access based parallel DSP processor for SDR and CR. - Andreas Karlsson; Joar Sohl; Jian Wang 035; Dake Liu (GlobalSIP, 2013)

Conflict-free data access for multi-bank memory architectures using padding. - Joar Sohl; Jian Wang 035; Andreas Karlsson; Dake Liu (HiPC, 2013)

Combined RF and multilevel PWM switch mode power amplifier. - Muhammad Fahim Ul Haque; Ted Johansson; Dake Liu (NORCHIP, 2013)

Efficient sorting design on a novel embedded parallel computing architecture with unique memory access. - Wenbiao Zhou; Zhaoyun Cai; Ruiqiang Ding; Chen Gong 003; Dake Liu (Comput. Electr. Eng., 2013)

Single instruction multiple data code auto generation for a very long instruction words digital signal processor in sensor-based systems. - Xu Yang 003; Yanjun Zhang; Dake Liu; Deyuan Guo; Hu He 001 (IET Wirel. Sens. Syst., 2013)

Application Specific Instruction Set DSP Processors. - Dake Liu; Jian Wang 035 (Handbook of Signal Processing Systems, 2013)

Flexible multistandard FEC processor design with ASIP methodology. - Zhenzhi Wu; Dake Liu (ASAP, 2014)

FPGA implementation of a multi-algorithm parallel FEC for SDR platforms. - Zhenzhi Wu; Dake Liu; Zheng Yang; Qingying Wang; Wei Zhou (FPL, 2014)

Matrix reordering techniques for memory conflict reduction for pipelined QC-LDPC decoder. - Zhenzhi Wu; Dake Liu; Yanjun Zhang (ICCC, 2014)

Recognition of access patterns for DSP kernel codes. - Xiaoyang Li; Yu Liu; Chen Gong 003; Dake Liu (ICSAI, 2014)

Memory sharing techniques for multi-standard high-throughput FEC decoder. - Zhenzhi Wu; Dake Liu (ICSAMOS, 2014)

A conflict-free access method for parallel turbo decoder. - Chen Gong 003; Xiaoyang Li; Zhenzhi Wu; Dake Liu (WCSP, 2014)

Comprehensive Performance Analysis of Two-Way Multi-Relay System with Amplify-and-Forward Relaying. - Siye Wang; Yanjun Zhang; Bo Zhou; Wenbiao Zhou; Dake Liu (IEICE Trans. Commun., 2014)

A Vision of IoT: Applications, Challenges, and Opportunities With China Perspective. - Shanzhi Chen; Hui Xu; Dake Liu; Bo Hu 003; Hucheng Wang (IEEE Internet Things J., 2014)

A novel transcutaneous NFC uplink system symbiotic with inductive wireless power supply under ultra low coupling coefficient. - Chen Gong 003; Dake Liu; Zhidong Miao; Huahong Zhang (BioCAS, 2015)

An optimizing procedure of the wireless power transfer link for an intraocular implantable device. - Zhidong Miao; Dake Liu; Chen Gong 003 (BMEI, 2015)

Combined RF and multiphase PWM transmitter. - Muhammad Fahim Ul Haque; Ted Johansson; Dake Liu (ECCTD, 2015)

Benefit and cost of cross sliding window scheduling for low latency 5G Turbo decoding. - Dake Liu; Chaoyuan Zuo; Zhenzhi Wu (ICCC, 2015)

ePUMA: A processor architecture for future DSP. - Andreas Karlsson; Joar Sohl; Dake Liu (DSP, 2015)

Cost-efficient mapping of 3- and 5-point DFTs to general baseband processors. - Andreas Karlsson; Joar Sohl; Dake Liu (DSP, 2015)

Software-based QPP interleaving for baseband DSPs with LUT-accelerated addressing. - Andreas Karlsson; Joar Sohl; Dake Liu (DSP, 2015)

High performance table-based architecture for parallel CRC calculation. - Yuanhong Huo; Xiaoyang Li; Wei Wang 128; Dake Liu (LANMAN, 2015)

A contention-free memory subsystem for 5G Turbo decoder with flexible degree of parallelism. - Zhenzhi Wu; Dake Liu; Xiaoyang Li; Chen Gong 003 (SiPS, 2015)

Loop acceleration and instruction repeat support for application specific instruction-set processors. - Zhenzhi Wu; Dake Liu; Xiaoyang Li (SoCC, 2015)

Energy-Efficient Sorting with the Distributed Memory Architecture ePUMA. - Andreas Karlsson; Joar Sohl; Dake Liu (TrustCom/BigDataSE/ISPA (3), 2015)

Virtual RATs and a flexible and tailored radio access network evolving to 5G. - Shanzhi Chen; Jian Zhao; Ming Ai; Dake Liu; Ying Peng (IEEE Commun. Mag., 2015)

High-Throughput Trellis Processor for Multistandard FEC Decoding. - Zhenzhi Wu; Dake Liu (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A digital crystal-less clock generation scheme for wireless biomedical implants. - Hongxia Luo; Dake Liu; Chen Gong 003; Min Li 006 (BioCAS, 2016)

A High-Throughput Processor for Cryptographic Hash Functions. - Yuanhong Huo; Dake Liu (J. Commun., 2016)

High-throughput area-efficient processor for 3GPP LTE cryptographic core algorithms. - Yuanhong Huo; Dake Liu (ASAP, 2017)

A 3-coil simultaneous power and uplink data transmission inductive link for battery-less implantable devices. - Min Li 006; Dake Liu; Chen Gong 003; Wan Qiao (ISCAS, 2017)

A Magnetic-Balanced Inductive Link for the Simultaneous Uplink Data and Power Telemetry. - Chen Gong 003; Dake Liu; Zhidong Miao; Min Li 006 (Sensors, 2017)

An NFC on Two-Coil WPT Link for Implantable Biomedical Sensors under Ultra-Weak Coupling. - Chen Gong 003; Dake Liu; Zhidong Miao; Wei Wang 128; Min Li 006 (Sensors, 2017)

An Adaptive Impedance Matching Network with Closed Loop Control Algorithm for Inductive Wireless Power Transfer. - Zhidong Miao; Dake Liu; Chen Gong 003 (Sensors, 2017)

Efficiency Enhancement for an Inductive Wireless Power Transfer System by Optimizing the Impedance Matching Networks. - Zhidong Miao; Dake Liu; Chen Gong 003 (IEEE Trans. Biomed. Circuits Syst., 2017)

Computational Complexity Analysis of FEC Decoding on SDR Platforms. - Zhenzhi Wu; Chen Gong 003; Dake Liu (J. Signal Process. Syst., 2017)

QFEC ASIP: A Flexible Quad-Mode FEC ASIP for Polar, LDPC, Turbo, and Convolutional Code Decoding. - Wan Qiao; Dake Liu; Shaohan Liu (IEEE Access, 2018)

High-throughput bit processor for cryptography, error correction, and error detection. - Yuanhong Huo; Dake Liu (Microprocess. Microsystems, 2018)

Design Space Exploration of 1-D FFT Processor. - Shaohan Liu; Dake Liu (J. Signal Process. Syst., 2018)

A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G. - Shaohan Liu; Dake Liu (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Design Space Exploration of SDR Vector Processor for 5G Micro Base Stations. - Wei Chen 100; Dake Liu; Yong Bai; Rifei Yang (IEEE Access, 2021)

An ASIP design for low loss compression of front-haul data in 5G base stations. - Yunxiang Tang; Biao Long; Dake Liu (IEICE Electron. Express, 2021)

Hardware Sharing for Channel Interleavers in 5G NR Standard. - Xiaokang Xiong; Yuhang Dai; Zhuhua Hu; Kejia Huo; Yong Bai; Hui Li 039; Dake Liu (Secur. Commun. Networks, 2021)

Low-Latency QC-LDPC Encoder Design for 5G NR. - Yunke Tian; Yong Bai; Dake Liu (Sensors, 2021)

Compilation of Parallel Data Access for Vector Processor in Radio Base Stations. - Wei Chen 100; Peng Hao; Dake Liu; Yong Bai (IEEE Embed. Syst. Lett., 2022)

An ASIP for Neural Network Inference on Embedded Devices with 99% PE Utilization and 100% Memory Hidden under Low Silicon Cost. - Muxuan Gao; He Chen 004; Dake Liu (Sensors, 2022)

An Uplink Channel Estimator Using a Dedicated Instruction Set for 5G Small Cells. - Biao Long; Dake Liu; Yipeng Sun (Sensors, 2022)

Detector Processor for a 5G Base Station. - Cao Niu; Dake Liu (Sensors, 2022)

TAPE: Tangible Augmented Previz Environment for Filmmaking. - Guangzheng Fei; Dake Liu (CCHI, 2023)

Conflict-Free Parallel Data Access Technology for Matrix Calculation in Memory System of ASIP of 5G/6G Macro Base Stations. - Wei Chen 100; Dake Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

B5G/6G URLLC Latency Reduction Method for Multisensor Industrial Internet of Things. - Wei Chen 100; Dake Liu; Yong Bai (IEEE Internet Things J., 2024)

AIKII: An AI-Enhanced Knowledge Interactive Interface for Knowledge Representation in Educational Games. - Dake Liu; Huiwen Zhao; Wen Tang; Wenwen Yang (Comput. Animat. Virtual Worlds, 2025)

High-Throughput LDPC Decoder for Multiple Wireless Standards. - Wei Chen 100; Yajie Li; Dake Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Hardware Sharing Design Method of Rate Matching and Interleaving for Wireless Terminal in Industrial Internet of Things. - Wei Chen 100; Kejia Huo; Dake Liu (IEEE Internet Things J., 2025)