Automatic Tuning Algorithms and Statistical Circuit Design - Dale E. Hocevar (1982)

A Study of Variance Reduction Techniques for Estimating Circuit Yields. - Dale E. Hocevar; Michael R. Lightner; Timothy N. Trick (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

An Extrapolated Yield Approximation Technique for Use in Yield Maximization. - Dale E. Hocevar; Michael R. Lightner; Timothy N. Trick (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984)

Transient Sensitivity Computation for MOSFET Circuits. - Dale E. Hocevar; Ping Yang 001; Timothy N. Trick; Berton D. Epler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985)

An Integrated and Efficient Approach for MOS VLSI Statistical Circuit Design. - Ping Yang 001; Dale E. Hocevar; Paul F. Cox; Charles F. Machala III; Pallab K. Chatterjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986)

SPIDER – A CAD System for Modeling VLSI Metallization Patterns. - Joseph E. Hall; Dale E. Hocevar; Ping Yang 001; Michael J. McGraw (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits. - Richard Burch; Farid N. Najm; Ping Yang 001; Dale E. Hocevar (DAC, 1988)

Parametric yield optimization for MOS circuit blocks. - Dale E. Hocevar; Paul F. Cox; Ping Yang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

New implicit integration method for efficient latency exploitation in circuit simulation. - Paul F. Cox; Richard Burch; Ping Yang 001; Dale E. Hocevar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

A Usable Circuit Optimizer for Designers. - Dale E. Hocevar; Rajeev Arora; Uttiya Dasgupta; Sattam Dasgupta; Nagaraj Subramanyam; Sham Kashyap (ICCAD, 1990)

Direct circuit simulation algorithms for parallel processing [VLSI]. - Paul F. Cox; Richard Burch; Dale E. Hocevar; Ping Yang 001; Berton D. Epler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Top-Down Design Using Cycle Based Simulation: an MPEG A/V Decoder Example. - Dale E. Hocevar; Ching-Yu Hung; Dan Pickens; Sundararajan Sriram (Great Lakes Symposium on VLSI, 1998)

Space-time codes with bit interleaving. - Tarik Muharemovic; Alan Gatherer; Will Ebel; Srinath Hosur; Dale E. Hocevar; Everest Huang (GLOBECOM, 2001)

Improving performance of a space-time turbo code in a Rayleigh fading channel. - Everest Huang; Alan Gatherer; Tarik Muharemovic; Dale E. Hocevar (VTC Fall, 2001)

600 MHz DSP for baseband processing in 3G base stations. - Tod Wolf; Dale E. Hocevar; Alan Gatherer; Patrick Geremia; Armelle Laine (CICC, 2002)

A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder. - Yanni Chen; Dale E. Hocevar (GLOBECOM, 2003)

Efficient encoding for a family of quasi-cyclic LDPC codes. - Dale E. Hocevar (GLOBECOM, 2003)

LDPC code construction with flexible hardware implementation. - Dale E. Hocevar (ICC, 2003)

A Reduced-Complexity, Scalable Implementation of Low Density Parity Check (LDPC) Decoder. - Yuming Zhu; Yanni Chen; Dale E. Hocevar; Manish Goel (SiPS, 2006)