Bottom-up digital system-level reliability modeling. - N. Ruiz Amador; Vincent Huard; E. Pion; Florian Cacho; Damien Croain; V. Robert; Sylvain Engels; Philippe Flatresse; Lorena Anghel (CICC, 2011)

Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec. - Julien Le Coz; Philippe Flatresse; Sylvain Engels; Alexandre Valentian; Marc Belleville; Christine Raynaud; Damien Croain; Pascal Urard (ISSCC, 2011)

28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors. - Fady Abouzeid; Sylvain Clerc; Cyril Bottoni; Benjamin Coeffic; Jean-Marc Daveau; Damien Croain; Gilles Gasiot; Dimitri Soussan; Philippe Roche (ESSCIRC, 2015)

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. - Sylvain Clerc; Mehdi Saligane; Fady Abouzeid; Martin Cochet; Jean-Marc Daveau; Cyril Bottoni; David Bol; Julien De Vos; Dominique Zamora; Benjamin Coeffic; Dimitri Soussan; Damien Croain; et al. (ISSCC, 2015)

A 28nm FD-SOI standard cell 0.6-1.2V open-loop frequency multiplier for low power SoC clocking. - Martin Cochet; Sylvain Clerc; Mehdi Naceur; Pierre Schamberger; Damien Croain; Jean-Luc Autran; Philippe Roche (ISCAS, 2016)

28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications. - Rossella Ranica; Nicolas Planes; Vincent Huard; Olivier Weber; Daniel Noblet; Damien Croain; Fabien Giner; Sylvie Naudet; P. Mergault; S. Ibars; A. Villaret; Maryline Parra; et al. (VLSI Circuits, 2016)

High-yield design of high-density SRAM for low-voltage and low-leakage operations. - Kedar Janardan Dhori; Hitesh Chawla; Ashish Kumar; Prashant Pandey; Promod Kumar; Lorenzo Ciampolini; Florian Cacho; Damien Croain (DFT, 2017)