Automatic stress effects computation based on a layout generation tool for analog IC. - Stephanie Youssef; Damien Dupuis; Ramy Iskander; Marie-Minerve Louërat (BMAS, 2010)

A seamless representation for coupling transistor sizing with nanometric CMOS layout generation. - Stephanie Youssef; Farakh Javid; Damien Dupuis; Ramy Iskander; Marie-Minerve Louërat (ECCTD, 2011)

A Python-based layout-aware analog design methodology for nanometric technologies. - Stephanie Youssef; Farakh Javid; Damien Dupuis; Ramy Iskander; Marie-Minerve Louërat (IDT, 2011)