Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy. - Lorena Anghel; Dan Alexandrescu; Michael Nicolaidis (SBCCI, 2000)

New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs. - Dan Alexandrescu; Lorena Anghel; Michael Nicolaidis (DFT, 2002)

Simulating Single Event Transients in VDSM ICs for Ground Level Radiation. - Dan Alexandrescu; Lorena Anghel; Michael Nicolaidis (J. Electron. Test., 2004)

A Systematical Method of Quantifying SEU FIT. - Shi-Jie Wen; Dan Alexandrescu; Renaud Perez (IOLTS, 2008)

Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors. - Michael Nicolaidis; Renaud Perez; Dan Alexandrescu (VTS, 2008)

Highs and lows of radiation testing. - Dan Alexandrescu; Anne-Lise Lhomme-Perrot; Erwin Schäfer; Cyrille Beltrando (IOLTS, 2009)

Panel: Reliability of data centers: Hardware vs. software. - Mehdi Baradaran Tahoori; Ishwar Parulkar; Dan Alexandrescu; Kevin Granlund; Allan Silburt; Bapi Vinnakota (DATE, 2010)

A Practical Approach to Single Event Transients Analysis for Highly Complex Designs. - Dan Alexandrescu; Enrico Costenaro; Michael Nicolaidis (DFT, 2011)

A comprehensive soft error analysis methodology for SoCs/ASICs memory instances. - Dan Alexandrescu (IOLTS, 2011)

A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories. - Enrico Costenaro; Massimo Violante; Dan Alexandrescu (IOLTS, 2011)

A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance. - Shrikanth Ganapathy; Ramon Canal; Dan Alexandrescu; Enrico Costenaro; Antonio González 001; Antonio Rubio 001 (ICCD, 2012)

Towards optimized functional evaluation of SEE-induced failures in complex designs. - Dan Alexandrescu; Enrico Costenaro (IOLTS, 2012)

RIIF - Reliability information interchange format. - Adrian Evans; Michael Nicolaidis; Shi-Jie Wen; Dan Alexandrescu; Enrico Costenaro (IOLTS, 2012)

A real-case application of a synergetic design-flow-oriented SER analysis. - Miguel Vilchis; Ramnath Venkatraman; Enrico Costenaro; Dan Alexandrescu (IOLTS, 2012)

Test methodology of a new upset mechanism induced by protons in deep sub-micron devices. - Cécile Weulersse; Florent Miller; Dan Alexandrescu; Erwin Schaefer; Olivier Crépel; Rémi Gaillard (Microelectron. Reliab., 2012)

State-aware single event analysis for sequential logic. - Dan Alexandrescu; Enrico Costenaro; Adrian Evans (IOLTS, 2013)

Hierarchical RTL-based combinatorial SER estimation. - Adrian Evans; Dan Alexandrescu; Enrico Costenaro; Liang Chen (IOLTS, 2013)

Pulse-length determination techniques in the rectangular single event transient fault model. - Alireza Rohani; Hans G. Kerkhoff; Enrico Costenaro; Dan Alexandrescu (ICSAMOS, 2013)

A Practical Approach to Single Event Transient Analysis for Highly Complex Design. - Enrico Costenaro; Dan Alexandrescu; Kader Belhaddad; Michael Nicolaidis (J. Electron. Test., 2013)

Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales. - Mojtaba Ebrahimi; Adrian Evans; Mehdi Baradaran Tahoori; Razi Seyyedi; Enrico Costenaro; Dan Alexandrescu (DATE, 2014)

INFORMER: An integrated framework for early-stage memory robustness analysis. - Shrikanth Ganapathy; Ramon Canal; Dan Alexandrescu; Enrico Costenaro; Antonio González 001; Antonio Rubio 001 (DATE, 2014)

Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation. - Dan Alexandrescu; Luca Sterpone; Celia López-Ongil (ETS, 2014)

Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. - Andreas Steininger; Varadan Savulimedu Veeravalli; Dan Alexandrescu; Enrico Costenaro; Lorena Anghel (ICCD, 2014)

Managing SER costs of complex systems through Linear Programming. - Dan Alexandrescu; Nematollah Bidokhti; Andy Yu; Adrian Evans; Enrico Costenaro (IOLTS, 2014)

New approaches for synthesis of redundant combinatorial logic for selective fault tolerance. - Hao Xie; Li Chen 001; Rui Liu 011; Adrian Evans; Dan Alexandrescu; Shi-Jie Wen; Rick Wong (IOLTS, 2014)

The future of fault tolerant computing. - Jacob A. Abraham; Ravishankar K. Iyer; Dimitris Gizopoulos; Dan Alexandrescu; Yervant Zorian (IOLTS, 2015)

A call for cross-layer and cross-domain reliability analysis and management. - Dan Alexandrescu; Adrian Evans; Enrico Costenaro; Maximilien Glorieux (IOLTS, 2015)

Techniques for heavy ion microbeam analysis of FPGA SER sensitivty. - Adrian Evans; Dan Alexandrescu; Veronique Ferlet-Cavrois; Kay-Obbe Voss (IRPS, 2015)

Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor. - Mojtaba Ebrahimi; Adrian Evans; Mehdi Baradaran Tahoori; Enrico Costenaro; Dan Alexandrescu; Vikas Chandra; Razi Seyyedi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer. - Dan Alexandrescu; Mustafa Altun; Lorena Anghel; Anna Bernasconi 001; Valentina Ciriani; Luca Frontini; Mehdi Baradaran Tahoori (DSD, 2016)

EDA support for functional safety - How static and dynamic failure analysis can improve productivity in the assessment of functional safety. - Dan Alexandrescu; Adrian Evans; Maximilien Glorieux; Issam Nofal (IOLTS, 2017)

Logic synthesis and testing techniques for switching nano-crossbar arrays. - Dan Alexandrescu; Mustafa Altun; Lorena Anghel; Anna Bernasconi 001; Valentina Ciriani; Luca Frontini; Mehdi Baradaran Tahoori (Microprocess. Microsystems, 2017)

A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs. - Luca Sterpone; Sarah Azimi; Ludovica Bozzoli; Boyang Du; Thomas Lange; Maximilien Glorieux; Dan Alexandrescu; Cesar Boatella Polo; David Merodio Codinachs (AHS, 2018)

Integrated Synthesis Methodology for Crossbar Arrays. - Muhammed Ceylan Morgül; Onur Tunali; Mustafa Altun; Luca Frontini; Valentina Ciriani; Elena-Ioana Vatajelu; Lorena Anghel; Csaba Andras Moritz; Mircea R. Stan; Dan Alexandrescu (NANOARCH, 2018)

Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors. - Aneesh Balakrishnan; Thomas Lange; Maximilien Glorieux; Dan Alexandrescu; Maksim Jenihhin (AHS, 2019)

Challenges of Reliability Assessment and Enhancement in Autonomous Systems. - Maksim Jenihhin; Matteo Sonza Reorda; Aneesh Balakrishnan; Dan Alexandrescu (DFT, 2019)

On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques. - Thomas Lange; Aneesh Balakrishnan; Maximilien Glorieux; Dan Alexandrescu; Luca Sterpone (DSN (Supplements), 2019)

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks. - Thomas Lange; Maximilien Glorieux; Dan Alexandrescu; Luca Sterpone (DTIS, 2019)

Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits. - Thomas Lange; Aneesh Balakrishnan; Maximilien Glorieux; Dan Alexandrescu; Luca Sterpone (IOLTS, 2019)

The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications. - Aneesh Balakrishnan; Thomas Lange; Maximilien Glorieux; Dan Alexandrescu; Maksim Jenihhin (NORCAS, 2019)

Understanding multidimensional verification: Where functional meets non-functional. - Xinhui Lai; Aneesh Balakrishnan; Thomas Lange; Maksim Jenihhin; Tara Ghasempouri; Jaan Raik; Dan Alexandrescu (Microprocess. Microsystems, 2019)

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. - Maksim Jenihhin; Said Hamdioui; Matteo Sonza Reorda; Milos Krstic; Peter Langendörfer; Christian Sauer 001; Anton Klotz; Michael Hübner 001; Jörg Nolte; Heinrich Theodor Vierhaus; Georgios N. Selimis; Dan Alexandrescu; et al. (DATE, 2020)

Enabling Cross-Layer Reliability and Functional Safety Assessment Through ML-Based Compact Models. - Dan Alexandrescu; Aneesh Balakrishnan; Thomas Lange; Maximilien Glorieux (IOLTS, 2020)

Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features. - Thomas Lange; Aneesh Balakrishnan; Maximilien Glorieux; Dan Alexandrescu; Luca Sterpone (IOLTS, 2020)

Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects. - Aneesh Balakrishnan; Thomas Lange; Maximilien Glorieux; Dan Alexandrescu; Maksim Jenihhin (MECO, 2020)

Modeling Soft-Error Reliability Under Variability. - Aneesh Balakrishnan; Guilherme Cardoso Medeiros; Cemil Cem Gürsoy; Said Hamdioui; Maksim Jenihhin; Dan Alexandrescu (DFT, 2021)

Gate-Level Graph Representation Learning: A Step Towards the Improved Stuck-at Faults Analysis. - Aneesh Balakrishnan; Dan Alexandrescu; Maksim Jenihhin; Thomas Lange; Maximilien Glorieux (ISQED, 2021)

On Antagonism Between Side-Channel Security and Soft-Error Reliability in BNN Inference Engines. - Xinhui Lai; Thomas Lange; Aneesh Balakrishnan; Dan Alexandrescu; Maksim Jenihhin (VLSI-SoC, 2021)

Innovation Practices Track: VLSI Functional Safety. - Fei Su; Meirav Nitzan; Ankush Sethi; Vaibhav Kumar; Dan Alexandrescu (VTS, 2023)