A 16-mW, 120-dB linear switched-capacitor delta-sigma modulator with dynamic biasing. - Dan B. Kasha; Wai L. Lee; Axel Thomsen (IEEE J. Solid State Circuits, 1999)

A 110-dB-THD, 18-mW DAC using sampling of the output and feedback to reduce distortion. - Axel Thomsen; Dan B. Kasha; Lei Wang; Wai L. Lee (IEEE J. Solid State Circuits, 1999)

A 2.5-Gb/s Multi-Rate 0.25-$ mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition. - Michael H. Perrott; Yunteng Huang; Rex T. Baird; Bruno W. Garlepp; Douglas Pastorello; Eric T. King; Qicheng Yu; Dan B. Kasha; Philip Steiner; Ligang Zhang; Jerrell P. Hein; Bruce Del Signore (IEEE J. Solid State Circuits, 2006)