Distributed scene graph to enable thousands of interacting users in a virtual environment. - Dan Lake; Mic Bowman; Huaiyu Liu (NETGAMES, 2010)

Scaling virtual worlds: Simulation requirements and challenges. - Huaiyu Liu; Mic Bowman; Robert Adams 003; John Hurliman; Dan Lake (WSC, 2010)

Navigating large data sets in virtual worlds. - Huaiyu Liu; Mic Bowman; Robert Adams 003; Dan Lake; Jerry Talton; Sean Koehl; Robert Noradki (VR, 2012)

A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. - Somnath Paul; Turbo Majumder; Charles Augustine; Andres F. Malavasi; S. Usirikayala; Raghavan Kumar; Jisna Kollikunnel; S. Chhabra; Satish Yada; M. L. Barajas; Carlos Ornelas; Dan Lake; et al. (VLSI Circuits, 2020)

A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses. - Saurabh Kumar 003; Minki Cho; Luke R. Everson; Andres Malavasi; Dan Lake; Carlos Tokunaga; Muhammad M. Khellah; James W. Tschanz; Vivek De; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup. - Somnath Kundu; Timo Huusari; Hao Luo; Abhishek Agrawal; Eduardo Alban; Sarah Shahraini; Thao Xiong; Dan Lake; Stefano Pellerano; Jason Mix; Nasser A. Kurd; Mohamed Abdel-moneum; et al. (ISSCC, 2022)

A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference. - Hechen Wang; Renzhi Liu; Richard Dorrance; Deepak Dasalukunte; Xiaosen Liu; Dan Lake; Brent R. Carlton; May Wu (VLSI Technology and Circuits, 2022)

A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference. - Hechen Wang; Renzhi Liu; Richard Dorrance; Deepak Dasalukunte; Dan Lake; Brent R. Carlton (IEEE J. Solid State Circuits, 2023)

System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution. - Srivatsa Rangachar Srinivasa; Dileep Kurian; Paolo A. Aseron; Prerna Budhkar; Vinayak Honkote; Dan Lake; Jaykant Timbadiya; Satish Yada; Suresh Kadavakollu; James Greensky; Gauthaman Murali; Anuradha Srinivasan; et al. (ACM Great Lakes Symposium on VLSI, 2025)

A 300MB SRAM, 20Tb/s Bandwidth Scalable Heterogenous 2.5D System Inferencing Simultaneous Streams Across 20 Chiplets with Workload-Dependent Configurations. - Srivatsa Rangachar Srinivasa; Dileep Kurian; Paolo A. Aseron; Prerna Budhkar; Arun Radhakrishnan; Alejandro Cardenas Lopez; Jainaveen Sundaram; Vinayak Honkote; Leonid Azarenkov; Dan Lake; Jaykant Timbadiya; Mikhail J. Moiseev; et al. (ISSCC, 2025)