Compiler-Directed Cache Line Size Adaptivity. - Dan Nicolaescu; Xiaomei Ji; Alexander V. Veidenbaum; Alexandru Nicolau; Rajesh K. Gupta 001 (Intelligent Memory Systems, 2000)

Compiler-Directed Cache Assist Adaptivity. - Xiaomei Ji; Dan Nicolaescu; Alexander V. Veidenbaum; Alexandru Nicolau; Rajesh K. Gupta 001 (ISHPC, 2000)

Low Energy Associative Data Caches for Embedded Systems. - Dan Nicolaescu; Alexander V. Veidenbaum; Alex Nicolau (Embedded Software for SoC, 2003)

Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors. - Dan Nicolaescu; Alexander V. Veidenbaum; Alexandru Nicolau (DATE, 2003)

Reducing data cache energy consumption via cached load/store queue. - Dan Nicolaescu; Alexander V. Veidenbaum; Alexandru Nicolau (ISLPED, 2003)

Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors. - Juan L. Aragón; Dan Nicolaescu; Alexander V. Veidenbaum; Ana-Maria Badulescu (DATE, 2004)

Low Energy, Highly-Associative Cache Design for Embedded Processors. - Alexander V. Veidenbaum; Dan Nicolaescu (ICCD, 2004)

Caching Values in the Load Store Queue. - Dan Nicolaescu; Alexander V. Veidenbaum; Alexandru Nicolau (MASCOTS, 2004)

Using a Way Cache to Improve Performance of Set-Associative Caches. - Dan Nicolaescu; Alexander V. Veidenbaum; Alexandru Nicolau (ISHPC, 2005)

Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy. - Dan Nicolaescu; Babak Salamat; Alexander V. Veidenbaum (ICCD, 2006)

The world's fastest DSP core: Breaking the 100 GMAC/s barrier. - Chris Rowen; Dan Nicolaescu; Rajiv Ravindran; David Heine; Grant Martin; James Kim; Dror E. Maydan; Nupur Andrews; Bill Huffman; Vakis Papaparaskeva; Shay Gal-On; Peter R. Nuth; et al. (Hot Chips Symposium, 2011)