Systematic Generation of Current-Mode Second Order RC Oscillators. - Dan Stiurca (ISCAS, 1994)

Sample-reset loop filter architecture for process independent and ripple-pole-less low jitter CMOS charge-pump PLLs. - Adrian Maxim; Baker Scott; Ed Schneider; Melvin Hagge; Steve Chacko; Dan Stiurca (ISCAS (4), 2001)

A low-jitter 125-1250-MHz process-independent and ripple-poleless 0.18-μm CMOS PLL based on a sample-reset loop filter. - Adrian Maxim; Baker Scott; Edmund M. Schneider; Melvin Hagge; Steve Chacko; Dan Stiurca (IEEE J. Solid State Circuits, 2001)

A fully differential line driver with on-chip calibrated source termination for gigabit and fast Ethernet in a standard 0.13µ CMOS process. - Dan Stiurca (ISCAS (3), 2005)