Sectors: Divide & Conquer and Softwarization in the Design and Validation of the Stratix® 10 FPGA. - Dana L. How; Sean Atsatt (FCCM, 2016)

Stratix™ 10 High Performance Routable Clock Networks. - Carl Ebeling; Dana How; David M. Lewis; Herman Schmit (FPGA, 2016)

3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration. - David Greenhill; Ron Ho; David M. Lewis; Herman Schmit; Kok Hong Chan; Andy Tong; Sean Atsatt; Dana How; Peter McElheny; Keith Duwel; Jeffrey Schulz; Darren Faulkner; et al. (ISSCC, 2017)

Architectural Enhancements in Intel® Agilex™ FPGAs. - Jeffrey Chromczak; Mark Wheeler; Charles Chiasson; Dana How; Martin Langhammer; Tim Vanderhoek; Grace Zgheib; Ilya Ganusov (FPGA, 2020)

Open-source and FPGAs: Hardware, Software, Both or None? - Dana How; Tim Ansell; Vaughn Betz; Chris Lavin; Ted Speers; Pierre-Emmanuel Gaillardon (FPGA, 2023)

From Topology to Realization in FPGA/VPR Routing. - Mahdi Abbaszadeh; Dana L. How (FPGA, 2024)