An SPU reference model for simulation, random test generation and verification. - Yukio Watanabe; Balazs Sallay; Brad W. Michael; Daniel A. Brokenshire; Gavin Meil; Hazim Shafi; Daisuke Hiraoka (ASP-DAC, 2006)

The microarchitecture of the synergistic processor for a cell processor. - Brian K. Flachs; Shigehiro Asano; Sang H. Dhong; H. Peter Hofstee; Gilles Gervais; Roy Kim; Tien Le; Peichun Liu; Jens Leenstra; John S. Liberty; Brad W. Michael; Hwa-Joon Oh; et al. (IEEE J. Solid State Circuits, 2006)

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. - Brian K. Flachs; Shigehiro Asano; Sang H. Dhong; H. Peter Hofstee; Gilles Gervais; Roy Kim; Tien Le; Peichun Liu; Jens Leenstra; John S. Liberty; Brad W. Michael; Hwa-Joon Oh; et al. (IBM J. Res. Dev., 2007)

Introduction to the Cell Broadband Engine Architecture. - Charles R. Johns; Daniel A. Brokenshire (IBM J. Res. Dev., 2007)

Petascale computing with accelerators. - Michael Kistler; John A. Gunnels; Daniel A. Brokenshire; Brad Benton (PPoPP, 2009)

Programming the Linpack benchmark for Roadrunner. - Michael Kistler; John A. Gunnels; Daniel A. Brokenshire; Brad Benton (IBM J. Res. Dev., 2009)

Programming the Linpack benchmark for the IBM PowerXCell 8i processor. - Michael Kistler; John A. Gunnels; Daniel A. Brokenshire; Brad Benton (Sci. Program., 2009)

Implementing FFTs on Multicore Architectures. - Alex Chung Hen Chow; Gordon C. Fossum; Daniel A. Brokenshire (Scientific Computing with Multicore and Accelerators, 2010)

Detecting race conditions in asynchronous DMA operations with full system simulation. - Michael Kistler; Daniel A. Brokenshire (ISPASS, 2011)