The impact of delay on the design of branch predictors. - Daniel A. Jiménez; Stephen W. Keckler; Calvin Lin (MICRO, 2000)

Boolean Formula-Based Branch Prediction for Future Technologies. - Daniel A. Jiménez; Heather L. Hanson; Calvin Lin (IEEE PACT, 2001)

Dynamic Branch Prediction with Perceptrons. - Daniel A. Jiménez; Calvin Lin (HPCA, 2001)

Neural methods for dynamic branch prediction. - Daniel A. Jiménez; Calvin Lin (ACM Trans. Comput. Syst., 2002)

Reconsidering Complex Branch Predictors. - Daniel A. Jiménez (HPCA, 2003)

Fast Path-Based Neural Branch Prediction. - Daniel A. Jiménez (MICRO, 2003)

Exploiting Procedure Level Locality to Reduce Instruction Cache Misses. - Ravi V. Batchu; Daniel A. Jiménez (Interaction between Compilers and Computer Architectures, 2004)

Toward an Evaluation Infrastructure for Power and Energy Optimizations. - Chunling Hu; Daniel A. Jiménez; Ulrich Kremer (IPDPS, 2005)

Piecewise Linear Branch Prediction. - Daniel A. Jiménez (ISCA, 2005)

Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor. - Miquel Pericàs; Adrián Cristal; Rubén González 001; Daniel A. Jiménez; Mateo Valero (ISHPC, 2005)

Code placement for improving dynamic branch prediction accuracy. - Daniel A. Jiménez (PLDI, 2005)

Chained In-Order/Out-of-Order DoubleCore Architecture. - Miquel Pericàs; Adrián Cristal; Rubén González 001; Daniel A. Jiménez (SBAC-PAD, 2005)

Idealized Piecewise Linear Branch Prediction. - Daniel A. Jiménez (J. Instr. Level Parallelism, 2005)

The Camino Compiler infrastructure. - Chunling Hu; John B. P. McCabe; Daniel A. Jiménez; Ulrich Kremer (SIGARCH Comput. Archit. News, 2005)

Improved latency and accuracy for neural branch prediction. - Daniel A. Jiménez (ACM Trans. Comput. Syst., 2005)

A decoupled KILO-instruction processor. - Miquel Pericàs; Adrián Cristal; Rubén González 001; Daniel A. Jiménez; Mateo Valero (HPCA, 2006)

Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors. - Daniel A. Jiménez; Gabriel H. Loh (SBAC-PAD, 2006)

A Flexible Heterogeneous Multi-Core Architecture. - Miquel Pericàs; Adrián Cristal; Francisco J. Cazorla; Rubén González 001; Daniel A. Jiménez; Mateo Valero (PACT, 2007)

Efficient Program Power Behavior Characterization. - Chunling Hu; Daniel A. Jiménez; Ulrich Kremer (HiPEAC, 2007)

An evaluation infrastructure for power and energy optimisations. - Chunling Hu; Daniel A. Jiménez; Ulrich Kremer (Int. J. Embed. Syst., 2007)

Guest Editor's Introduction. - Daniel A. Jiménez (J. Instr. Level Parallelism, 2007)

A Two-Level Load/Store Queue Based on Execution Locality. - Miquel Pericàs; Adrián Cristal; Francisco J. Cazorla; Rubén González 001; Alexander V. Veidenbaum; Daniel A. Jiménez; Mateo Valero (ISCA, 2008)

Low-power, high-performance analog neural branch prediction. - Renée St. Amant; Daniel A. Jiménez; Doug Burger (MICRO, 2008)

Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors. - Gabriel H. Loh; Daniel A. Jiménez (Int. J. Parallel Program., 2008)

Composite Confidence Estimators for Enhanced Speculation Control. - Daniel A. Jiménez (SBAC-PAD, 2009)

Mixed-Signal Approximate Computation: A Neural Predictor Case Study. - Renée St. Amant; Daniel A. Jiménez; Doug Burger (IEEE Micro, 2009)

Generalizing neural branch prediction. - Daniel A. Jiménez (ACM Trans. Archit. Code Optim., 2009)

Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization. - Chunling Hu; Daniel A. Jiménez; Ulrich Kremer (Trans. High Perform. Embed. Archit. Compil., 2009)

Using dead blocks as a virtual victim cache. - Samira Manabi Khan; Daniel A. Jiménez; Doug Burger; Babak Falsafi (PACT, 2010)

Insertion policy selection using Decision Tree Analysis. - Samira Manabi Khan; Daniel A. Jiménez (ICCD, 2010)

Sampling Dead Block Prediction for Last-Level Caches. - Samira Manabi Khan; Yingying Tian; Daniel A. Jiménez (MICRO, 2010)

Decoupled Cache Segmentation: Mutable Policy with Automated Bypass. - Samira Manabi Khan; Daniel A. Jiménez (PACT, 2011)

Sampling Temporal Touch Hint (STTH) Inclusive Cache Management Policy. - Yingying Tian; Daniel A. Jiménez (PACT, 2011)

Program Interferometry. - Zhe Wang 023; Daniel A. Jiménez (PACT, 2011)

Exploiting Rank Idle Time for Scheduling Last-Level Cache Writeback. - Zhe Wang 023; Daniel A. Jiménez (PACT, 2011)

An optimized scaled neural branch predictor. - Daniel A. Jiménez (ICCD, 2011)

Reducing network-on-chip energy consumption through spatial locality speculation. - Hyungjun Kim; Pritha Ghoshal; Boris Grot; Paul V. Gratz; Daniel A. Jiménez (NOCS, 2011)

Decoupled dynamic cache segmentation. - Samira Manabi Khan; Zhe Wang 023; Daniel A. Jiménez (HPCA, 2012)

Improving writeback efficiency with decoupled last-write prediction. - Zhe Wang 023; Samira Manabi Khan; Daniel A. Jiménez (ISCA, 2012)

Rank idle time prediction driven last-level cache writeback. - Zhe Wang 023; Samira Manabi Khan; Daniel A. Jiménez (MSPC, 2012)

B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors. - Reena Panda; Paul V. Gratz; Daniel A. Jiménez (IEEE Comput. Archit. Lett., 2012)

Improving multi-core performance using mixed-cell cache architecture. - Samira Manabi Khan; Alaa R. Alameldeen; Chris Wilkerson; Jaydeep Kulkarni; Daniel A. Jiménez (HPCA, 2013)

Insertion and promotion for tree-based PseudoLRU last-level caches. - Daniel A. Jiménez (MICRO, 2013)

Temporal-based multilevel correlating inclusive cache replacement. - Yingying Tian; Samira Manabi Khan; Daniel A. Jiménez (ACM Trans. Archit. Code Optim., 2013)

WADE: Writeback-aware dynamic cache management for NVM-based main memory system. - Zhe Wang 023; Shuchang Shan; Ting Cao; Junli Gu; Yi Xu; Shuai Mu; Yuan Xie 001; Daniel A. Jiménez (ACM Trans. Archit. Code Optim., 2013)

Improving cache performance using read-write partitioning. - Samira Manabi Khan; Alaa R. Alameldeen; Chris Wilkerson; Onur Mutlu; Daniel A. Jiménez (HPCA, 2014)

Adaptive placement and migration policy for an STT-RAM-based hybrid cache. - Zhe Wang 023; Daniel A. Jiménez; Cong Xu 002; Guangyu Sun 003; Yuan Xie 001 (HPCA, 2014)

Last-level cache deduplication. - Yingying Tian; Samira Manabi Khan; Daniel A. Jiménez; Gabriel H. Loh (ICS, 2014)

B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors. - David Kadjo; Jinchun Kim; Prabal Sharma; Reena Panda; Paul Gratz; Daniel A. Jiménez (MICRO, 2014)

Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip. - Hyungjun Kim; Boris Grot; Paul V. Gratz; Daniel A. Jiménez (IEEE Trans. Computers, 2014)

Adaptive GPU cache bypassing. - Yingying Tian; Sooraj Puthoor; Joseph L. Greathouse; Bradford M. Beckmann; Daniel A. Jiménez (GPGPU@PPoPP, 2015)

Minimal disturbance placement and promotion. - Elvira Teran; Yingying Tian; Zhe Wang 023; Daniel A. Jiménez (HPCA, 2016)

Perceptron learning for reuse prediction. - Elvira Teran; Zhe Wang 023; Daniel A. Jiménez (MICRO, 2016)

Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor. - Zhe Wang 023; Daniel A. Jiménez; Tao Zhang 032; Gabriel H. Loh; Yuan Xie 001 (SBAC-PAD, 2016)

Sensible Energy Accounting with Abstract Metering for Multicore Systems. - Qixiao Liu; Miquel Moretó; Jaume Abella 001; Francisco J. Cazorla; Daniel A. Jiménez; Mateo Valero (ACM Trans. Archit. Code Optim., 2016)

Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy. - Jinchun Kim; Elvira Teran; Paul V. Gratz; Daniel A. Jiménez; Seth H. Pugsley; Chris Wilkerson (ASPLOS, 2017)

Multiperspective reuse prediction. - Daniel A. Jiménez; Elvira Teran (MICRO, 2017)

Flexible associativity for DRAM caches. - Elvira Teran; Zeshan Chishti; Zhe Wang 023; Chris Wilkerson; Daniel A. Jiménez (CF, 2018)

Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer. - Samira Mirbagher Ajorpaz; Elba Garza; Sangam Jindal; Daniel A. Jiménez (ISCA, 2018)

MTB-Fetch: Multithreading Aware Hardware Prefetching for Chip Multiprocessors. - Laith M. AlBarakat; Paul V. Gratz; Daniel A. Jiménez (IEEE Comput. Archit. Lett., 2018)

Perceptron-based prefetch filtering. - Eshan Bhatia; Gino Chacon; Seth H. Pugsley; Elvira Teran; Paul V. Gratz; Daniel A. Jiménez (ISCA, 2019)

Bit-level perceptron prediction for indirect branches. - Elba Garza; Samira Mirbagher Ajorpaz; Tahsin Ahmad Khan; Daniel A. Jiménez (ISCA, 2019)

The impact of cache inclusion policies on cache management techniques. - Luna Backes; Daniel A. Jiménez (MEMSYS, 2019)

LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. - Behzad Salami 001; Konstantinos Parasyris; Adrián Cristal; Osman S. Unsal; Xavier Martorell; Paul Carpenter; Raúl de la Cruz; Leonardo Bautista-Gomez; Daniel A. Jiménez; Carlos Álvarez 001; S. Nabavi; Sergi Madonar; et al. (CoRR, 2019)

LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. - Behzad Salami 001; Konstantinos Parasyris; Adrián Cristal; Osman S. Unsal; Xavier Martorell; Paul Carpenter; Raúl de la Cruz; Leonardo Bautista-Gomez; Daniel A. Jiménez; Carlos Álvarez 001; Seyed Saber Nabavi Larimi; Sergi Madonar; et al. (DATE, 2020)

SB-Fetch: synchronization aware hardware prefetching for chip multiprocessors. - Laith M. AlBarakat; Paul V. Gratz; Daniel A. Jiménez (ICS, 2020)

Characterizing the impact of last-level cache replacement policies on big-data workloads. - Alexandre Valentin Jamet; Lluc Alvarez; Daniel A. Jiménez; Marc Casas (IISWC, 2020)

Evolution of the Samsung Exynos CPU Microarchitecture. - Brian Grayson; Jeff Rupley; Gerald D. Zuraski; Eric Quinnell; Daniel A. Jiménez; Tarun Nakra; Paul Kitchin; Ryan Hensley; Edward Brekelbaum; Vikas Sinha; Ankit Ghiya (ISCA, 2020)

Support for Diverse Students. - Daniel A. Jiménez (KDD, 2020)

CHiRP: Control-Flow History Reuse Prediction. - Samira Mirbagher Ajorpaz; Elba Garza; Gilles Pokam; Daniel A. Jiménez (MICRO, 2020)

PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron. - Samira Mirbagher Ajorpaz; Gilles Pokam; Esmaeil Mohammadian Koruyeh; Elba Garza; Nael B. Abu-Ghazaleh; Daniel A. Jiménez (MICRO, 2020)

Exploiting Page Table Locality for Agile TLB Prefetching. - Georgios Vavouliotis; Lluc Alvarez; Vasileios Karakostas; Konstantinos Nikas; Nectarios Koziris; Daniel A. Jiménez; Marc Casas (ISCA, 2021)

Morrigan: A Composite Instruction TLB Prefetcher. - Georgios Vavouliotis; Lluc Alvarez; Boris Grot; Daniel A. Jiménez; Marc Casas (MICRO, 2021)

Top Picks From the 2020 Computer Architecture Conferences. - Daniel A. Jiménez (IEEE Micro, 2021)

SLAP-CC: Set-Level Adaptive Prefetching for Compressed Caches. - Laith M. AlBarakat; Paul V. Gratz; Daniel A. Jiménez (ICCD, 2022)

Composite Instruction Prefetching. - Gino Chacon; Elba Garza; Alexandra Jimborean; Alberto Ros 001; Paul V. Gratz; Daniel A. Jiménez; Samira Mirbagher Ajorpaz (ICCD, 2022)

Thermometer: profile-guided btb replacement for data center applications. - Shixin Song; Tanvir Ahmed Khan; Sara Mahdizadeh-Shahri; Akshitha Sriraman; Niranjan K. Soundararajan; Sreenivas Subramoney; Daniel A. Jiménez; Heiner Litz; Baris Kasikci (ISCA, 2022)

Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications. - Tanvir Ahmed Khan; Muhammed Ugur; Krishnendra Nathella; Dam Sunwoo; Heiner Litz; Daniel A. Jiménez; Baris Kasikci (MICRO, 2022)

Page Size Aware Cache Prefetching. - Georgios Vavouliotis; Gino Chacon; Lluc Alvarez; Paul V. Gratz; Daniel A. Jiménez; Marc Casas (MICRO, 2022)

Dynamic Set Stealing to Improve Cache Performance. - Brady Testa; Samira Mirbagher Ajorpaz; Daniel A. Jiménez (SBAC-PAD, 2022)

The Championship Simulator: Architectural Simulation for Education and Competition. - Nathan Gober; Gino Chacon; Lei Wang; Paul V. Gratz; Daniel A. Jiménez; Elvira Teran; Seth H. Pugsley; Jinchun Kim (CoRR, 2022)

Rebasing Microarchitectural Research with Industry Traces. - Josué Feliu; Arthur Perais; Daniel A. Jiménez; Alberto Ros 001 (IISWC, 2023)

A Characterization of the Effects of Software Instruction Prefetching on an Aggressive Front-end. - Gino Chacon; Nathan Gober; Krishnendra Nathella; Paul V. Gratz; Daniel A. Jiménez (ISPASS, 2023)

Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching. - Daniel A. Jiménez; Elvira Teran; Paul V. Gratz (IEEE Comput. Archit. Lett., 2023)

A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering. - Alexandre Valentin Jamet; Georgios Vavouliotis; Daniel A. Jiménez; Lluc Alvarez; Marc Casas (HPCA, 2024)

Practically Tackling Memory Bottlenecks of Graph-Processing Workloads. - Alexandre Valentin Jamet; Georgios Vavouliotis; Daniel A. Jiménez; Lluc Alvarez; Marc Casas (IPDPS, 2024)

Message from the MICRO 2024 Program Chairs. - Daniel A. Jiménez; Alaa R. Alameldeen (MICRO, 2024)

Correct Wrong Path. - Bhargav Reddy Godala; Sankara Prasad Ramesh; Krishnam Tibrewala; Chrysanthos Pepi; Gino Chacon; Svilen Kanev; Gilles A. Pokam; Daniel A. Jiménez; Paul V. Gratz; David I. August (CoRR, 2024)

Exposing Shadow Branches. - Chrysanthos Pepi; Bhargav Reddy Godala; Krishnam Tibrewala; Gino Chacon; Paul V. Gratz; Daniel A. Jiménez; Gilles A. Pokam; David I. August (CoRR, 2024)

Instruction-Aware Cooperative TLB and Cache Replacement Policies. - Dimitrios Chasapis; Georgios Vavouliotis; Daniel A. Jiménez; Marc Casas (ASPLOS (1), 2025)

Skia: Exposing Shadow Branches. - Chrysanthos Pepi; Bhargav Reddy Godala; Krishnam Tibrewala; Gino A. Chacon; Paul V. Gratz; Daniel A. Jiménez; Gilles A. Pokam; David I. August (ASPLOS (2), 2025)

Light-weight Cache Replacement for Instruction Heavy Workloads. - Saba Mostofi; Setu Gupta; Ahmad Hassani; Krishnam Tibrewala; Elvira Teran; Paul V. Gratz; Daniel A. Jiménez (ISCA, 2025)

Correct Wrong Path. - Bhargav Reddy Godala; Sankara Prasad Ramesh; Krishnam Tibrewala; Chrysanthos Pepi; Gino Chacon; Svilen Kanev; Gilles A. Pokam; Alberto Ros 001; Daniel A. Jiménez; Paul V. Gratz; David I. August (IEEE Comput. Archit. Lett., 2025)