FSPICE: a tool for fault modelling in MOS circuits. - Michel Renovell; Gaston Cambon; Daniel Auvergne (Integr., 1985)

Path runner: an accurate and fast timing analyser. - Denis Deschacht; P. Pinede; Michel Robert; Daniel Auvergne (EURO-DAC, 1990)

Input waveform slope effects in CMOS delays. - Daniel Auvergne; Nadine Azémard; Denis Deschacht; Michel Robert (IEEE J. Solid State Circuits, 1990)

Formal sizing rules of CMOS circuits. - Daniel Auvergne; Nadine Azémard; V. Bonzom; Denis Deschacht; Michel Robert (EURO-DAC, 1991)

TVA: A timing verifier with analytic temporal modelling. - D. Navarro; A. Roy; Michel Robert; Denis Deschacht; Daniel Auvergne (Microprocessing and Microprogramming, 1991)

Synchronous-mode evaluation of delays in CMOS structures. - Denis Deschacht; Michel Robert; Daniel Auvergne (IEEE J. Solid State Circuits, 1991)

P.SIZE: a sizing aid for optimized designs. - Nadine Azémard; V. Bonzom; Daniel Auvergne (EURO-DAC, 1992)

Post-layout timing simulation of CMOS circuits. - Denis Deschacht; Michel Robert; Nadine Azémard-Crestani; Daniel Auvergne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Influence of Locig Block Layout Architecture on FPGA Performance. - Michel Robert; Lionel Torres; Fernando Moraes 001; Daniel Auvergne (FPL, 1994)

Delay modelling improvement for low voltage applications. - Jean Michel Daga; Michel Robert; Daniel Auvergne (EURO-DAC, 1995)

Explicit evaluation of short circuit power dissipation for CMOS logic structures. - S. Turgis; Nadine Azémard; Daniel Auvergne (ISLPD, 1995)

Design and selection of buffers for minimum power-delay product. - S. Turgis; Nadine Azémard; Daniel Auvergne (ED&TC, 1996)

Delay propagation effect in transistor gates. - Denis Deschacht; Christophe Dabrin; Daniel Auvergne (IEEE J. Solid State Circuits, 1996)

Internal power modelling and minimization in CMOS inverters. - S. Turgis; Jean Michel Daga; Josep M. Portal; Daniel Auvergne (ED&TC, 1997)

Temperature Effect on Delay for Low Voltage Applications. - Jean Michel Daga; E. Ottaviano; Daniel Auvergne (DATE, 1998)

A novel macromodel for power estimation in CMOS structures. - S. Turgis; Daniel Auvergne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Delay-power performance analysis. - S. Cremoux; M. Aline; Nadine Azémard; Daniel Auvergne (ICECS, 1999)

RF Interface Design Using Mixed-Mode Methodology. - Augusto Gallegos; Philippe Silvestre; Michel Robert; Daniel Auvergne (VLSI, 1999)

A Virtual CMOS Library Approach for East Layout Synthesis. - Fernando Moraes 001; Michel Robert; Daniel Auvergne (VLSI, 1999)

A comprehensive delay macro modeling for submicrometer CMOS logics. - Jean Michel Daga; Daniel Auvergne (IEEE J. Solid State Circuits, 1999)

Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions. - Jean Michel Daga; Caroline Papaix; Marc Merandat; Stephane Ricard; Giuseppe Medulla; Jeanine Guichaoua; Daniel Auvergne (MTDT, 2000)

Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design. - Philippe Maurine; Mustapha Rezzoug; Daniel Auvergne (PATMOS, 2000)

Second Generation Delay Model for Submicron CMOS Process. - Mustapha Rezzoug; Philippe Maurine; Daniel Auvergne (PATMOS, 2000)

Feasible Delay Bound Definition. - Nadine Azémard; M. Aline; Philippe Maurine; Daniel Auvergne (VLSI-SOC, 2001)

Gate Sizing for Low Power Design. - Philippe Maurine; Nadine Azémard; Daniel Auvergne (VLSI-SOC, 2001)

Delay bound determination for timing closure satisfaction. - Nadine Azémard; M. Aline; Daniel Auvergne (ISCAS (5), 2001)

Output transition time modeling of CMOS structures. - Philippe Maurine; Mustapha Rezzoug; Daniel Auvergne (ISCAS (5), 2001)

POPS: A tool for delay/power performance optimization. - Nadine Azémard; Daniel Auvergne (J. Syst. Archit., 2001)

Gate speed improvement at minimal power dissipation. - Philippe Maurine; Xavier Michel; Nadine Azémard; Daniel Auvergne (APCCAS (2), 2002)

Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications. - Wenceslas Rahajandraibe; Christian Dufaza; Daniel Auvergne; Bruno Cialdella; Bernard Majoux; Vivek Chowdhury (DATE, 2002)

Transistor Level Synthesis Dedicated to Fast I.P. Prototyping. - Alexis Landrault; Ludovic Pellier; Alexandre Richard; Christian Jay; Michel Robert; Daniel Auvergne (PATMOS, 2002)

Structure Independent Representation of Output Transition Time for CMOS Library. - Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2002)

Crosstalk Measurement Technique for CMOS ICs. - Fabrice Picot; Philippe Coll; Daniel Auvergne (PATMOS, 2002)

Transition time modeling in deep submicron CMOS. - Philippe Maurine; Mustapha Rezzoug; Nadine Azémard; Daniel Auvergne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Continuous representation of the performance of a CMOS library. - B. Lasbouygues; Joel Schindler; Sylvain Engels; Philippe Maurine; Nadine Azémard; Daniel Auvergne (ESSCIRC, 2003)

Metric Definition for Circuit Speed Optimization. - Xavier Michel; Alexandre Verle; Nadine Azémard; Philippe Maurine; Daniel Auvergne (PATMOS, 2003)

CMOS Gate Sizing under Delay Constraint. - Alexandre Verle; Xavier Michel; Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2003)

Design Techniques for EEPROMs Embedded in Portable Systems on Chips. - Jean Michel Daga; Caroline Papaix; Marc Merandat; Stephane Ricard; Giuseppe Medulla; Jeanine Guichaoua; Daniel Auvergne (IEEE Des. Test Comput., 2003)

Delay bound based CMOS gate sizing technique. - Alexandre Verle; Xavier Michel; Philippe Maurine; Nadine Azémard; Daniel Auvergne (ISCAS (5), 2004)

Design Optimization with Automated Cell Generation. - A. Landrault; Nadine Azémard; Philippe Maurine; Michel Robert; Daniel Auvergne (PATMOS, 2004)

Temperature Dependence in Low Power CMOS UDSM Process. - B. Lasbouygues; Robin Wilson; Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2004)

Physical Extension of the Logical Effort Model. - B. Lasbouygues; Robin Wilson; Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2004)

Performance Metric Based Optimization Protocol. - Xavier Michel; Alexandre Verle; Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2004)

Low Power Oriented CMOS Circuit Optimization Protocol. - Alexandre Verle; Xavier Michel; Nadine Azémard; Philippe Maurine; Daniel Auvergne (DATE, 2005)

Logical effort model extension to propagation delay representation. - B. Lasbouygues; Sylvain Engels; Robin Wilson; Philippe Maurine; Nadine Azémard; Daniel Auvergne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)