Memory aspects in signal processing and HLS tool: Some results. - Jean Luc Philippe; Daniel Chillet; Olivier Sentieys; Jean-Philippe Diguet (EUSIPCO, 1996)

VLSI high level synthesis of fast exact least mean square algorithms based on fast FIR filters. - Jean-Philippe Diguet; Olivier Sentieys; Daniel Chillet; Jean Luc Philippe (ICASSP, 1997)

Asynchronous timing model for high-level synthesis of DSP applications. - J. Okito Dedou; Daniel Chillet; Olivier Sentieys (EUSIPCO, 1998)

Memory Unit Design for Real Time DSP Applications. - Daniel Chillet; Olivier Sentieys; Michel Corazza (Great Lakes Symposium on VLSI, 1999)

Behavioral synthesis of asynchronous systems: a methodology. - J. O. Dedou; Daniel Chillet; Olivier Sentieys (ISCAS (6), 1999)

Multi-algorithm ASIP synthesis and power estimation for DSP applications. - Jean-Gabriel Cousin; Olivier Sentieys; Daniel Chillet (ISCAS, 2000)

Teaching hardware/software system codesign using CAD tools: a case study in image synthesis. - Hélène Dubois; Olivier Sentieys; Daniel Chillet; Jean Luc Philippe (IEEE Trans. Educ., 2000)

A Framework for High Level Estimations of Signal Processing VLSI Implementations. - Jean-Philippe Diguet; Daniel Chillet; Olivier Sentieys (J. VLSI Signal Process., 2000)

A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals. - Raphaël David; Daniel Chillet; Sébastien Pillement; Olivier Sentieys (VLSI-SOC, 2001)

Automatic floating-point to fixed-point conversion for DSP code generation. - Daniel Ménard; Daniel Chillet; François Charot; Olivier Sentieys (CASES, 2002)

A Compilation Framework for a Dynamically Reconfigurable Architecture. - Raphaël David; Daniel Chillet; Sébastien Pillement; Olivier Sentieys (FPL, 2002)

Mapping future generation mobile telecommunication applications on a dynamically reconfigurable arcidtecture. - Raphaël David; Daniel Chillet; Sébastien Pillement; Olivier Sentieys (ICASSP, 2002)

DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints. - Raphaël David; Daniel Chillet; Sébastien Pillement; Olivier Sentieys (IPDPS, 2002)

Behavioral IP Specification and Integration Framework for High-Level Design Reuse. - Sébastien Pillement; Daniel Chillet; Olivier Sentieys (ISQED, 2002)

Implantation d'algorithmes spécifiés en virgule flottante dans les DSP virgule fixe. - Daniel Ménard; Taofik Saïdi; Daniel Chillet; Olivier Sentieys (Tech. Sci. Informatiques, 2003)

Co-Design of Massively Parallel Embedded Processor Architectures. - Frank Hannig; Hritam Dutta; Alexey Kupriyanov; Jürgen Teich; Rainer Schaffer; Sebastian Siegel; Renate Merker; Ronan Keryell; Bernard Pottier; Daniel Chillet; Daniel Ménard; Olivier Sentieys (ReCoSoC, 2005)

Exploring RTOS issues with a high-level model of a reconfigurable SoC platform. - François Verdier; Jean-Christophe Prévotet; Mohamed El Amine Benkhelifa; Daniel Chillet; Sébastien Pillement (ReCoSoC, 2005)

Floating-to-Fixed-Point Conversion for Digital Signal Processors. - Daniel Ménard; Daniel Chillet; Olivier Sentieys (EURASIP J. Adv. Signal Process., 2006)

Hardware task scheduling for heterogeneous soc architectures. - Imene Benkermi; Daniel Chillet; Sébastien Pillement; Olivier Sentieys (EUSIPCO, 2007)

A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures. - Daniel Chillet; Sébastien Pillement; Olivier Sentieys (IJCNN, 2007)

A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources. - Jean-Christophe Prévotet; Mohamed El Amine Benkhelifa; Bertrand Granado; Emmanuel Huck; Benoît Miramond; François Verdier; Daniel Chillet; Sébastien Pillement (ReConFig, 2008)

Structure mémoire reconfigurable. Vers une structure de stockage faible consommation. - Daniel Chillet; Raphaël David; Erwan Grâce; Olivier Sentieys (Tech. Sci. Informatiques, 2008)

High-Level Exploration for Dynamic Reconfiguration Management. - Sébastien Pillement; Daniel Chillet; Yaset Oliva; Jean-Christophe Prévotet (ERSA, 2009)

OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms. - Benoît Miramond; Emmanuel Huck; François Verdier; Mohamed El Amine Benkhelifa; Bertrand Granado; Thomas LeFebvre; Mehdi Aïchouch; Jean-Christophe Prévotet; Yaset Oliva; Daniel Chillet; Sébastien Pillement (Int. J. Reconfigurable Comput., 2009)

Task placement for dynamic and partial reconfigurable architecture. - Antoine Eiche; Daniel Chillet; Sébastien Pillement; Olivier Sentieys (DASIP, 2010)

Open-People: Open Power and Energy Optimization PLatform and Estimator. - Daniel Chillet (PATMOS, 2010)

R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip. - Ludovic Devaux; Sébastien Pillement; Daniel Chillet; Didier Demigny (ReConFig, 2010)

Mesh and Fat-Tree comparison for dynamically reconfigurable applications. - Ludovic Devaux; Sébastien Pillement; Daniel Chillet; Didier Demigny (ReCoSoC, 2010)

Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures. - Ludovic Devaux; Sana Ben Sassi; Sébastien Pillement; Daniel Chillet; Didier Demigny (Int. J. Reconfigurable Comput., 2010)

Parallel Evaluation of Hopfield Neural Networks. - Antoine Eiche; Daniel Chillet; Sébastien Pillement; Olivier Sentieys (IJCCI (NCTA), 2011)

Hardware OS Communication Service and Dynamic Memory Management for RSoCs. - Surya Narayanan; Daniel Chillet; Sébastien Pillement; Ioannis Sourdis (ReConFig, 2011)

Towards a power and energy efficient use of partial dynamic reconfiguration. - Robin Bonamy; Daniel Chillet; Olivier Sentieys; Sébastien Bilavarn (ReCoSoC, 2011)

Communication service for hardware tasks executed on dynamic and partial reconfigurable resources. - Surya Narayanan; Ludovic Devaux; Daniel Chillet; Sébastien Pillement; Ioannis Sourdis (VLSI-SoC, 2011)

AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC. - Dominique Blouin; Daniel Chillet; Eric Senn; Sébastien Bilavarn; Robin Bonamy; Christian Samoyeau (Int. J. Reconfigurable Comput., 2011)

Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network. - Daniel Chillet; Antoine Eiche; Sébastien Pillement; Olivier Sentieys (J. Syst. Archit., 2011)

Parallelism Level Impact on Energy Consumption in Reconfigurable Devices. - Robin Bonamy; Daniel Chillet; Olivier Sentieys; Sébastien Bilavarn (SIGARCH Comput. Archit. News, 2011)

Open-people: An open platform for estimation and optimizations of energy consumption. - Eric Senn; Daniel Chillet; Olivier Zendra; Cécile Belleudy; Rabie Ben Atitallah; A. Fritsch; Christian Samoyeau (DASIP, 2012)

UPaRC - Ultra-fast power-aware reconfiguration controller. - Robin Bonamy; Hung-Manh Pham; Sébastien Pillement; Daniel Chillet (DATE, 2012)

Open-People: Open Power and Energy Optimization PLatform and Estimator. - Eric Senn; Daniel Chillet; Olivier Zendra; Cécile Belleudy; Sébastien Bilavarn; Rabie Ben Atitallah; Christian Samoyeau; A. Fritsch (DSD, 2012)

Power consumption model for partial and dynamic reconfiguration. - Robin Bonamy; Daniel Chillet; Sébastien Bilavarn; Olivier Sentieys (ReConFig, 2012)

Communication cost reduction for hardware tasks placed on homogeneous reconfigurable resource. - Quang-Hai Khuat; Daniel Chillet (DASIP, 2013)

Spatio-temporal scheduling for 3D reconfigurable & multiprocessor architecture. - Quang-Hai Khuat; Quang-Hoa Le; Daniel Chillet; Sébastien Pillement (IDT, 2013)

An Efficient Framework for Power-Aware Design of Heterogeneous MPSoC. - Rabie Ben Atitallah; Eric Senn; Daniel Chillet; Mickael Lanoe; Dominique Blouin (IEEE Trans. Ind. Informatics, 2013)

Considering reconfiguration overhead in scheduling of dependent tasks on 2D reconfigurable FPGA. - Quang-Hai Khuat; Daniel Chillet; Michael Hübner 001 (AHS, 2014)

Intrinsic Fault Tolerance of Hopfield Artificial Neural Network Model for Task Scheduling Technique in SoC. - Rajhans Singh; Daniel Chillet (IJCCI (NCTA), 2014)

Dynamic run-time hardware/software scheduling for 3D reconfigurable SoC. - Quang-Hai Khuat; Daniel Chillet; Michael Hübner 001 (ReConFig, 2014)

Special issue on design and architectures of real-time image processing in embedded systems. - Daniel Chillet; Michael Hübner 001 (J. Real Time Image Process., 2014)

Power consumption models for the use of dynamic and partial reconfiguration. - Robin Bonamy; Sébastien Bilavarn; Daniel Chillet; Olivier Sentieys (Microprocess. Microsystems, 2014)

Channel Allocation Protocol for Reconfigurable Optical Network-on-Chip. - Jiating Luo; Cédric Killian; Sébastien Le Beux; Daniel Chillet; Hui Li 034; Ian O'Connor; Olivier Sentieys (SiPhotonics@HiPEAC, 2015)

Communication Aware Design Method for Optical Network-on-Chip. - Johanna Sepúlveda; Sébastien Le Beux; Jiating Luo; Cédric Killian; Daniel Chillet; Hui Li 034; Ian O'Connor; Olivier Sentieys (MCSoC, 2015)

New Pack Oriented Solutions for Energy-Aware Feasible Adaptive Real-Time Systems. - Aymen Gammoudi 002; Adel Benzina; Mohamed Khalgui; Daniel Chillet (SoMeT, 2015)

Real-Time Scheduling of Reconfigurable Battery-Powered Multi-Core Platforms. - Aymen Gammoudi 002; Adel Benzina; Mohamed Khalgui; Daniel Chillet (ICTAI, 2016)

Power Modeling and Exploration of Dynamic and Partially Reconfigurable Systems. - Robin Bonamy; Sébastien Bilavarn; Daniel Chillet; Olivier Sentieys (J. Low Power Electron., 2016)

Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques. - Cédric Killian; Daniel Chillet; Sébastien Le Beux; Van-Dung Pham; Olivier Sentieys; Ian O'Connor (DAC, 2017)

Performance and energy aware wavelength allocation on ring-based WDM 3D optical NoC. - Jiating Luo; A. Elantably; Van-Dung Pham; Cédric Killian; Daniel Chillet; Sébastien Le Beux; Olivier Sentieys; Ian O'Connor (DATE, 2017)

Run-Time management of energy-performance trade-off in Optical Network-on-Chip. - Jiating Luo; Van-Dung Pham; Cédric Killian; Daniel Chillet; Ian O'Connor; Olivier Sentieys; Sébastien Le Beux (DCIS, 2018)

Mapping of Periodic Tasks in Reconfigurable Heterogeneous Multi-core Platforms. - Aymen Gammoudi 002; Daniel Chillet; Mohamed Khalgui; Adel Benzina (ENASE, 2018)

Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects. - Jiating Luo; Cédric Killian; Sébastien Le Beux; Daniel Chillet; Olivier Sentieys; Ian O'Connor (ACM J. Emerg. Technol. Comput. Syst., 2018)

Approximate nanophotonic interconnects. - Jaechul Lee; Cédric Killian; Sébastien Le Beux; Daniel Chillet (NOCS, 2019)

Multiple Permanent Faults Mitigation Through Bit-Shuffling for Network-an-Chip Architecture. - Romain Mercier; Cédric Killian; Angeliki Kritikakou; Youri Helen; Daniel Chillet (ICCD, 2020)

Energy-Efficient Scheduling of Real-Time Tasks in Reconfigurable Homogeneous Multicore Platforms. - Aymen Gammoudi 002; Adel Benzina; Mohamed Khalgui; Daniel Chillet (IEEE Trans. Syst. Man Cybern. Syst., 2020)

A Region-Based Bit-Shuffling Approach Trading Hardware Cost and Fault Mitigation Efficiency. - Romain Mercier; Cédric Killian; Angeliki Kritikakou; Youri Helen; Daniel Chillet (DFT, 2021)

Data and Fault Aware Routing Algorithm for NoC Based Approximate Computing. - Ibrahim Krayem; Romain Mercier; Cédric Killian; Angeliki Kritikakou; Daniel Chillet (NANOARCH, 2022)

BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation. - Romain Mercier; Cédric Killian; Angeliki Kritikakou; Youri Helen; Daniel Chillet (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Distance-aware Approximate Nanophotonic Interconnect. - Jaechul Lee; Cédric Killian; Sébastien Le Beux; Daniel Chillet (ACM Trans. Design Autom. Electr. Syst., 2022)

Analytical Model for Performance Evaluation of Token-Passing-Based WiNoCs. - Ibrahim Krayem; Joel Ortiz Sosa; Cédric Killian; Daniel Chillet (IEEE Des. Test, 2023)

FPGA-based CNN Acceleration using Pattern-Aware Pruning. - Léo Pradels; Silviu-Ioan Filip; Olivier Sentieys; Daniel Chillet; Thibaut Le Calloch (AICAS, 2024)

HTAG-eNN: Hardening Technique with AND Gates for Embedded Neural Networks. - Wilfread Guillemé; Angeliki Kritikakou; Youri Helen; Cédric Killian; Daniel Chillet (DAC, 2024)

VANDOR: Mitigating SEUs into Quantized Neural Networks. - Wilfread Guillemé; Angeliki Kritikakou; Youri Helen; Cédric Killian; Daniel Chillet (IOLTS, 2024)

Mitigation of Hardware Trojan in NoC using Delta-Based Compression. - Hamza Amara; Cédric Killian; Daniel Chillet; Emmanuel Casseau (SOCC, 2024)

Fault Tolerance in Quantized and Pruned Convolutional Neural Networks. - Wilfread Guillemé; Angeliki Kritikakou; Youri Helen; Cédric Killian; Daniel Chillet (IOLTS, 2025)

Empirical Analysis and Estimation of the Energy Cost of Data Transfers in CPU Caches in Multi-Core Systems. - Gaëtan Barret; Joël Penhoat; Roland Picard; Daniel Chillet (MECO, 2025)

Towards Accurate Static Power Model on Multi-Core Operating Systems. - Gaëtan Barret; Daniel Chillet; Roland Picard; Joël Penhoat (RAPIDO@HiPEAC, 2025)