A 200-MHz 64-bit Dual-Issue CMOS Microprocessor. - Daniel W. Dobberpuhl; Richard T. Witek; Randy L. Allmon; Robert Anglin; David Bertucci; Sharon M. Britton; Linda Chao; Robert A. Conrad; Daniel E. Dever; Bruce Gieseke; Soha Hassoun; Gregory W. Hoeppner; et al. (Digit. Tech. J., 1992)

A 200-MHz 64-b dual-issue CMOS microprocessor. - Daniel W. Dobberpuhl; Richard T. Witek; Randy L. Allmon; Robert Anglin; David Bertucci; Sharon M. Britton; Linda Chao; Robert A. Conrad; Daniel E. Dever; Bruce Gieseke; Soha Hassoun; Gregory W. Hoeppner; et al. (IEEE J. Solid State Circuits, 1992)

Internal Organization of the Alpha 21164, a 300-MHz 64-bit Quad-issue CMOS RISC Microprocessor - John H. Edmondson; Paul I. Rubinfeld; Peter J. Bannon; Bradley J. Benschneider; Debra Bernstein; Ruben W. Castelino; Elizabeth M. Cooper; Daniel E. Dever; Dale R. Donchin; Timothy C. Fischer; Anil K. Jain 003; Shekhar Mehta; et al. (Digit. Tech. J., 1995)

A 300-MHz 64-b quad-issue CMOS RISC microprocessor. - Bradley J. Benschneider; Andrew J. Black; William J. Bowhill; Sharon M. Britton; Daniel E. Dever; Dale R. Donchin; Robert J. Dupcak; Richard M. Fromm; Mary K. Gowan; Paul E. Gronowski; Michael Kantrowitz; Marc E. Lamere; et al. (IEEE J. Solid State Circuits, 1995)

Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU. - Joel Grodstein; Rachid Rayess; Tad Truex; Linda Shattuck; Sue Lowell; Dan Bailey; David Bertucci; Gabriel P. Bischoff; Daniel E. Dever; Mike Gowan; Roy Lane; Brian Lilly; et al. (ACM Great Lakes Symposium on VLSI, 2002)