An interconnect-driven design of a DFT processor. - Daniel Eckerbert; Henrik Eriksson; Per Larsson-Edefors; Anders Edman (ISCAS, 2000)

Interconnect-Driven Short-Circuit Power Modeling. - Daniel Eckerbert; Per Larsson-Edefors (DSD, 2001)

Cycle-true leakage current modeling for CMOS gates. - Daniel Eckerbert; Per Larsson-Edefors (ISCAS (5), 2001)

A deep submicron power estimation methodology adaptable to variations between power characterization and estimation. - Daniel Eckerbert; Per Larsson-Edefors (ASP-DAC, 2003)

A Mixed-Mode Delay-Locked-Loop Architecture. - Daniel Eckerbert; Lars J. Svensson; Per Larsson-Edefors (ICCD, 2003)

Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. - Per Larsson-Edefors; Daniel Eckerbert; Henrik Eriksson; Lars J. Svensson (ISVLSI, 2003)

A power cut-off technique for gate leakage suppression [CMOS logic circuits]. - Mindaugas Draidiiulis; Per Larsson-Edefors; Daniel Eckerbert; Henrik Eriksson (ESSCIRC, 2004)

Toward architecture-based test-vector generation for timing verification of fast parallel multipliers. - Henrik Eriksson; Per Larsson-Edefors; Daniel Eckerbert (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A 4.75-34.75 MHz digitally tunable active-RC LPF for >60dB mean RX IRR in 65nm CMOS. - Martin Anderson; Roland Strandberg; Staffan Ek; Leif R. Wilhelmsson; Lars Sundström; Mattias Andersson 003; Imad ud Din; Jim Svensson; Thomas Olsson 001; Daniel Eckerbert (ESSCIRC, 2012)

A receiver for LTE Rel-11 and beyond supporting non-contiguous carrier aggregation. - Lars Sundström; Martin Anderson; Roland Strandberg; Staffan Ek; Jim Svensson; Fenghao Mu; Thomas Olsson 001; Imad ud Din; Leif R. Wilhelmsson; Daniel Eckerbert; Sven Mattisson (ISSCC, 2013)

Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS. - Lars Sundström; Staffan Ek; Jim Svensson; Martin Anderson; Roland Strandberg; Fenghao Mu; Imad ud Din; Thomas Olsson 001; Leif R. Wilhelmsson; Daniel Eckerbert (IEEE J. Solid State Circuits, 2013)

A Wideband Sub-6-GHz Transceiver Front End for 5G Base Stations in 22-nm FD-SOI CMOS. - Christian Elgaard; Mohammed Abdulaziz; Tony Påhlsson; Bengt Edholm; Florent Torres; Fabien Mesquita; Martin Hansson; Daniel Eckerbert; Stefan Back Andersson; Sven Mattisson; Henrik Sjöland (IEEE J. Solid State Circuits, 2025)