Switch-Level Logic Simulation of Digital Bipolar Circuits. - Ibrahim N. Hajj; Daniel G. Saab (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Delay Modeling and Time of Bipolar Digital Circuits. - Daniel G. Saab; Andrew T. Yang; Ibrahim N. Hajj (DAC, 1988)

CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits. - Daniel G. Saab; Robert B. Mueller-Thuns; David T. Blaauw; Jacob A. Abraham; Joseph T. Rahmeh (ICCAD, 1988)

Automatic Generation of Behavioral Models from Switch-Level Descriptions. - David T. Blaauw; Daniel G. Saab; Robert B. Mueller-Thuns; Jacob A. Abraham; Joseph T. Rahmeh (DAC, 1989)

Portable parallel logic and fault simulation. - Robert B. Mueller-Thuns; Daniel G. Saab; Robert F. Damiano; Jacob A. Abraham (ICCAD, 1989)

Parallel-concurrent fault simulation. - Daniel G. Saab; Ibrahim N. Hajj; Joseph T. Rahmeh (ICCD, 1989)

Derivation of signal flow for switch-level simulation. - David T. Blaauw; Daniel G. Saab; Junsheng Long; Jacob A. Abraham (EURO-DAC, 1990)

SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. - David T. Blaauw; Robert B. Mueller-Thuns; Daniel G. Saab; Prithviraj Banerjee; Jacob A. Abraham (ICCAD, 1990)

Fault grading of large digital systems. - Daniel G. Saab; Robert B. Mueller-Thuns; David T. Blaauw; Joseph T. Rahmeh; Jacob A. Abraham (ICCD, 1990)

Design of a scalable parallel switch-level simulator for VLSI. - Robert B. Mueller-Thuns; Daniel G. Saab; Jacob A. Abraham (SC, 1990)

Hierarchical multi-level fault simulation of large systems. - Daniel G. Saab; Robert B. Mueller-Thuns; David T. Blaauw; Joseph T. Rahmeh; Jacob A. Abraham (J. Electron. Test., 1990)

Functional abstraction of logic gates for switch-level simulation. - David T. Blaauw; Daniel G. Saab; Prithviraj Banerjee; Jacob A. Abraham (EURO-DAC, 1991)

Parallel switch-level simulation for VLSI. - Robert B. Mueller-Thuns; Daniel G. Saab; Jacob A. Abraham (EURO-DAC, 1991)

BETA: Behavioral Testability Analysis. - Chung-Hsing Chen; Chienwen Wu; Daniel G. Saab (ICCAD, 1991)

Accessibility Analysis on Data Flow Graph: An Approach to Design for Testability. - Chung-Hsing Chen; Chienwen Wu; Daniel G. Saab (ICCD, 1991)

Fault modeling and testing of self-timed circuits. - Stanford S. Guillory; Daniel G. Saab; Andrew T. Yang (VTS, 1991)

Behavioral synthesis for testability. - Chung-Hsing Chen; Daniel G. Saab (ICCAD, 1992)

CRIS: a test cultivation program for sequential VLSI circuits. - Daniel G. Saab; Youssef Saab; Jacob A. Abraham (ICCAD, 1992)

Hierarchical Simulation of MOS Circuits Using Extracted Functional Models. - Jalal A. Wehbeh; Daniel G. Saab (ICCD, 1992)

Database Recovery Using Redundant Disk Arrays. - Antoine N. Mourad; W. Kent Fuchs; Daniel G. Saab (ICDE, 1992)

Site Partitioning for Distributed Redundant Disk Arrays. - Antoine N. Mourad; W. Kent Fuchs; Daniel G. Saab (RIDE-TQP, 1992)

Robust switch-level test generation. - Ben Mathew; Daniel G. Saab (VTS, 1992)

Fault behavior dictionary for simulation of device-level transients. - Gwan S. Choi; Ravishankar K. Iyer; Daniel G. Saab (ICCAD, 1993)

Augmented partial reset. - Ben Mathew; Daniel G. Saab (ICCAD, 1993)

Assigning Sites fto Redundant Clusters in a Distributed Storage System. - Antoine N. Mourad; W. Kent Fuchs; Daniel G. Saab (ICPP (1), 1993)

Performance of Redundant Disk Array Organizations in Transaction Processing Environments. - Antoine N. Mourad; W. Kent Fuchs; Daniel G. Saab (ICPP (1), 1993)

On Selecting Flip-Flops for Partial Reset. - Miron Abramovici; Prashant S. Parikh; Ben Mathew; Daniel G. Saab (ITC, 1993)

CHEETA: Composition of Hierarchical Sequential Tests Using ATKET. - Praveen Vishakantaiah; Jacob A. Abraham; Daniel G. Saab (ITC, 1993)

Recovery Issues in Databases Using Redundant Disk Arrays. - Antoine N. Mourad; W. Kent Fuchs; Daniel G. Saab (J. Parallel Distributed Comput., 1993)

Concurrent Hierarchical and Multilevel Simulation of VLSI Circuits. - Robert B. Mueller-Thuns; Joseph T. Rahmeh; Jacob A. Abraham; Jalal A. Wehbeh; Daniel G. Saab (Simul., 1993)

A novel behavioral testability measure. - Chung-Hsing Chen; Daniel G. Saab (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

VLSI logic and fault simulation on general-purpose parallel computers. - Robert B. Mueller-Thuns; Daniel G. Saab; Robert F. Damiano; Jacob A. Abraham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Switch-level timing simulation of bipolar ECL circuits. - Andrew T. Yang; Yu-Hsu Chang; Daniel G. Saab; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Benchmarking Parallel Processing Platforms: An Applications Perspective. - Robert B. Mueller-Thuns; Daniel G. Saab; Robert F. Damiano; Jacob A. Abraham (IEEE Trans. Parallel Distributed Syst., 1993)

Parallel-concurrent fault simulation. - Daniel G. Saab (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. - Elizabeth M. Rudnick; John G. Holm; Daniel G. Saab; Janak H. Patel (EDAC-ETC-EUROASIC, 1994)

Efficient simulation of switch-level circuits in a hierarchical simulation environment. - Jalal A. Wehbeh; Daniel G. Saab (Great Lakes Symposium on VLSI, 1994)

Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0. - Daniel G. Saab; Youssef Saab; Jacob A. Abraham (ICCAD, 1994)

On the Initialization of Sequential Circuits. - Jalal A. Wehbeh; Daniel G. Saab (ITC, 1994)

Structural and behavioral synthesis for testability techniques. - Chung-Hsing Chen; Tanay Karnik; Daniel G. Saab (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Partial Reset: An Alternative DFT Approach. - Ben Mathew; Daniel G. Saab (VLSI Design, 1994)

DFT & ATPG: Together Again. - Ben Mathew; Daniel G. Saab (ITC, 1995)

Site Partitioning for Redundant Arrays of Distributed Disks. - Antoine N. Mourad; W. Kent Fuchs; Daniel G. Saab (J. Parallel Distributed Comput., 1996)

Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms. - Daniel G. Saab; Youssef Saab; Jacob A. Abraham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Satisfiability on reconfigurable hardware. - Miron Abramovici; Daniel G. Saab (FPL, 1997)

Dynamic fault diagnosis for sequential circuits on reconfigurable hardware. - Fatih Kocan; Daniel G. Saab (ICCD, 1998)

Initialization of Sequential Circuits and its Application to ATPG. - Jalal A. Wehbeh; Daniel G. Saab (J. Electron. Test., 1998)

A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware. - Miron Abramovici; José T. de Sousa; Daniel G. Saab (DAC, 1999)

Dynamic Fault Diagnosis on Reconfigurable Hardware. - Fatih Kocan; Daniel G. Saab (DAC, 1999)

Concurrent D-algorithm on reconfigurable hardware. - Fatih Kocan; Daniel G. Saab (ICCAD, 1999)

Combining multiple DFT schemes with test generation. - Ben Mathew; Daniel G. Saab (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA. - Tarachand Pagarani; Fatih Kocan; Daniel G. Saab; Jacob A. Abraham (CICC, 2000)

Hierarchical Test Generation for Systems On a Chip. - Raghuram S. Tupuri; Jacob A. Abraham; Daniel G. Saab (VLSI Design, 2000)

ATPG for combinational circuits on configurable hardware. - Fatih Kocan; Daniel G. Saab (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Massively Parallel/Reconfigurable Emulation Model for the D-algorithm. - Daniel G. Saab; Fatih Kocan; Jacob A. Abraham (FPL, 2002)

Verifying Properties Using Sequential ATPG. - Jacob A. Abraham; Vivekananda M. Vedula; Daniel G. Saab (ITC, 2002)

Correction to "ATPG for combinational circuits on configurable hardware". - Fatih Kocan; Daniel G. Saab (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines. - Daniel G. Saab; Jacob A. Abraham; Vivekananda M. Vedula (VLSI Design, 2003)

An Emulation Model for Sequential ATPG-Based Bounded Model Checking. - Qiang Qiang; Daniel G. Saab; Jacob A. Abraham (FPL, 2005)

Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core. - Qiang Qiang; Chia-Lun Chang; Daniel G. Saab; Jacob A. Abraham (ICCD, 2005)

HDL Program Slicing to Reduce Bounded Model Checking Search Overhead. - Jen-Chieh Ou; Daniel G. Saab; Jacob A. Abraham (ITC, 2006)

Checking Nested Properties Using Bounded Model Checking and Sequential ATPG. - Qiang Qiang; Daniel G. Saab; Jacob A. Abraham (VLSI Design, 2006)

Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches. - Swarup Bhunia; Massood Tabib-Azar; Daniel G. Saab (ASP-DAC, 2007)

Critical Path Delay Reduction in FPGAs with Unbalanced Lookup Times. - Jason Meyer; Fatih Kocan; Daniel G. Saab (ERSA, 2007)

Automatic Generation of Instructions to Robustly Test Delay Defects in Processors. - Sankar Gurumurthy; Ramtilak Vemu; Jacob A. Abraham; Daniel G. Saab (ETS, 2007)

Reducing verification overhead with RTL slicing. - Jen-Chieh Ou; Daniel G. Saab; Qiang Qiang; Jacob A. Abraham (ACM Great Lakes Symposium on VLSI, 2007)

Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs. - Jacob A. Abraham; Daniel G. Saab (VLSI Design, 2007)

Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware. - Fatih Kocan; Daniel G. Saab (J. Electron. Test., 2007)

Complementary nano-electromechanical switches for ultra-low power embedded processors. - Khawla Alzoubi; Daniel G. Saab; Massood Tabib-Azar (ACM Great Lakes Symposium on VLSI, 2009)

Exact Path Delay Fault Coverage Calculation of Partitioned Circuits. - Fatih Kocan; Lun Li; Daniel G. Saab (IEEE Trans. Computers, 2009)

Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA. - Vijay K. Sirigir; Khawla Alzoubi; Daniel G. Saab; Fatih Kocan; Massood Tabib-Azar (FPL, 2010)

Complementary Nano-Electro-Mechanical Switch for ultra-low-power applications: Design and modeling. - Khawla Alzoubi; Daniel G. Saab; Sijing Han; Massood Tabib-Azar (ISQED, 2011)

Ultra-low power NEMS FPGA. - Sijing Han; Vijay Sirigiri; Daniel G. Saab; Massood Tabib-Azar (ICCAD, 2012)

Formal Verification ATPG Search Engine Emulator (Abstract Only). - Gregory Ford; Aswin Krishna; Jacob A. Abraham; Daniel G. Saab (FPGA, 2015)

Single Trojan injection model generation and detection. - Harini Bhamidipati; Daniel G. Saab; Jacob A. Abraham (LATS, 2016)

Automatic Assertion Generation for Simulation, Formal Verification and Emulation. - Tong Zhang; Daniel G. Saab; Jacob A. Abraham (ISVLSI, 2017)

ESIFT: Efficient System for Error Injection. - Ninghan Tian; Daniel G. Saab; Jacob A. Abraham (IOLTS, 2018)