Design of arithmetic elements for Burroughs Scientific Processor. - Daniel D. Gajski; Louis P. Rubinfield (IEEE Symposium on Computer Arithmetic, 1978)

Automatic design with dependence graphs. - Albert E. Casavant; Daniel D. Gajski; David J. Kuck (DAC, 1980)

Parallel Compressors. - Daniel Gajski (IEEE Trans. Computers, 1980)

Recurrence semigroups and their relation to data storage in fast recurrence solvers on parallel machines. - Daniel Gajski (CONPAR, 1981)

Automatic generation of cells for recurrence structures. - Avinoam Bilgory; Daniel D. Gajski (DAC, 1981)

Design of Testable Structures Defined by Simple Loops. - Jacob A. Abraham; Daniel Gajski (IEEE Trans. Computers, 1981)

An Algorithm for Solving Linear Recurrence Systems on Parallel and Pipelined Machines. - Daniel Gajski (IEEE Trans. Computers, 1981)

Iterative algorithms for tridiagonal matrices on a WSI-multiprocessor. - Daniel D. Gajski; Ahmed H. Sameh; John A. Wisniewski (ICPP, 1982)

A Second Opinion on Data Flow Machines and Languages. - Daniel Gajski; David A. Padua; David J. Kuck; Robert H. Kuhn (Computer, 1982)

New VLSI Tools - Guest Editors' Introduction. - Daniel Gajski; Robert H. Kuhn (Computer, 1983)

CEDAR: a large scale multiprocessor. - Daniel Gajski; David J. Kuck; Duncan H. Lawrie; Ahmed H. Sameh (SIGARCH Comput. Archit. News, 1983)

Cedar. - Daniel D. Gajski; Duncan H. Lawrie; David J. Kuck; Ahmed H. Sameh (COMPCON, 1984)

Silicon compilers and expert systems for VLSI. - Daniel D. Gajski (DAC, 1984)

Cell compilation with constraints. - Chidchanok Lursinsap; Daniel Gajski (DAC, 1984)

Microprocessor synthesis. - Vijay K. Raj; Barry M. Pangrle; Daniel D. Gajski (DAC, 1984)

A Parallel Pipelined Relational Query Processor: An Architectural Overview. - Daniel Gajski; Won Kim 001; Shinya Fushimi (ISCA, 1984)

Fast Execution of Loops with IF Statements. - Utpal Banerjee; Daniel Gajski (IEEE Trans. Computers, 1984)

A Parallel Pipelined Relational Query Processor. - Won Kim 001; Daniel Gajski; David J. Kuck (ACM Trans. Database Syst., 1984)

Decomposition of logic networks into silicon. - Steven T. Healey; Daniel D. Gajski (DAC, 1985)

Essential Issues in Multiprocessor Systems. - Daniel Gajski; Jih-Kwon Peir (Computer, 1985)

Comparison of five multiprocessor systems. - Daniel Gajski; Jih-Kwon Peir (Parallel Comput., 1985)

An expert-system paradigm for design. - Forrest Brewer; Daniel Gajski (DAC, 1986)

Flow graph representation. - Alex Orailoglu; Daniel Gajski (DAC, 1986)

CAMP: A Programming Aide for Multiprocessors. - Jih-Kwon Peir; Daniel Gajski (ICPP, 1986)

A Heuristic for Suffix Solutions. - Avinoam Bilgory; Daniel Gajski (IEEE Trans. Computers, 1986)

Knowledge Based Control in Micro-Architecture Design. - Forrest Brewer; Daniel Gajski (DAC, 1987)

Improving a PLA Area by Pull-Up Transistor Folding. - Chidchanok Lursinsap; Daniel Gajski (DAC, 1987)

A Programming Aid for Message-passing Systems. - Min-You Wu; Daniel Gajski (PP, 1987)

Design Tools for Intelligent Silicon Compilation. - Barry M. Pangrle; Daniel D. Gajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

MILO: A Microarchitecture and Logic Optimizer. - Nels Vander Zanden; Daniel Gajski (DAC, 1988)

Synthesis from VHDL. - Joseph Lis; Daniel D. Gajski (ICCD, 1988)

LES: a layout expert system. - Youn-Long Lin; Daniel D. Gajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

A technique for pull-up transistor folding. - Chidchanok Lursinsap; Daniel D. Gajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

A programming aid for hypercube architectures. - Min-You Wu; Daniel D. Gajski (J. Supercomput., 1988)

Designer Controlled Behavioral Synthesis. - Nikil D. Dutt; Daniel Gajski (DAC, 1989)

VHDL Synthesis Using Structured Modeling. - Joseph Lis; Daniel Gajski (DAC, 1989)

Hypertool: A Programming Aid for Multicomputers. - Min-You Wu; Daniel Gajski (ICPP (2), 1989)

Power routing in channelless floorplan layouts. - Chidchanok Lursinsap; Daniel Gajski (Integr., 1989)

Computer-aided programming for message-passing systems: problems and solutions. - Min-You Wu; Daniel D. Gajski (Proc. IEEE, 1989)

An Intelligent Component Database for Behavioral Synthesis. - Gwo-Dong Chen; Daniel Gajski (DAC, 1990)

An Intermediate Representation for Behavioral Synthesis. - Nikil D. Dutt; Tedd Hadley; Daniel Gajski (DAC, 1990)

Percolation Based Synthesis. - Roni Potasman; Joseph Lis; Alexandru Nicolau; Daniel Gajski (DAC, 1990)

Silicon compilation of switched: capacitor networks. - Mehrdad Negahban; Daniel Gajski (EURO-DAC, 1990)

A new algorithm for transistor sizing in CMOS circuits. - Allen C.-H. Wu; Nels Vander Zanden; Daniel Gajski (EURO-DAC, 1990)

The Component Sythesis Algorithm: Technology Mapping for Register Transfer Descriptions. - Elke A. Rundensteiner; Daniel Gajski; Lubomir Bic (ICCAD, 1990)

Design Synthesis and Silicon Compilation. - Nikil D. Dutt; Daniel D. Gajski (IEEE Des. Test Comput., 1990)

The Role of Learning in Logic Synthesis. - James R. Kipps; Daniel D. Gajski (Int. J. Pattern Recognit. Artif. Intell., 1990)

Chippe: a system for constraint driven behavioral synthesis. - Forrest Brewer; Daniel D. Gajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Hypertool: A Programming Aid for Message-Passing Systems. - Min-You Wu; Daniel Gajski (IEEE Trans. Parallel Distributed Syst., 1990)

Translating system specifications to VHDL. - Sanjiv Narayan; Frank Vahid; Daniel D. Gajski (EURO-DAC, 1991)

Glue-logic partitioning for floorplans with a rectilinear datapath. - Allen C.-H. Wu; Daniel D. Gajski (EURO-DAC, 1991)

System Specification and Synthesis with the SpecCharts Language. - Sanjiv Narayan; Frank Vahid; Daniel Gajski (ICCAD, 1991)

An Algorithm for Component Selection in Performance Optimized Scheduling. - Loganath Ramachandran; Daniel Gajski (ICCAD, 1991)

Obtaining Functionally Equivalent Simulations using VHDL and a Time-Shift Transformation. - Frank Vahid; Daniel Gajski (ICCAD, 1991)

Layout-Area Models for High-Level Synthesis. - Allen C.-H. Wu; Viraphol Chaiyakul; Daniel Gajski (ICCAD, 1991)

Youn-Long Steve Lin - Daniel D. Gajski; Nikil D. Dutt; Allen C.-H. Wu (Springer, 1992)

Functional Synthesis Using Area and Delay Optimization. - Elke A. Rundensteiner; Daniel Gajski (DAC, 1992)

Specification Partitioning for System Design. - Frank Vahid; Daniel Gajski (DAC, 1992)

Timing models for high-level synthesis. - Viraphol Chaiyakul; Allen C.-H. Wu; Daniel D. Gajski (EURO-DAC, 1992)

System clock estimation based on clock slack minimization. - Sanjiv Narayan; Daniel D. Gajski (EURO-DAC, 1992)

Semantics and synthesis of signals in behavioral VHDL. - Loganath Ramachandran; Frank Vahid; Sanjiv Narayan; Daniel D. Gajski (EURO-DAC, 1992)

An effective methodology for functional pipelining. - Tsing-Fa Lee; Allen C.-H. Wu; Daniel Gajski; Youn-Long Lin (ICCAD, 1992)

Accurate layout area and delay modeling for system level design. - Champaka Ramachandran; Fadi J. Kurdahi; Daniel Gajski; Allen C.-H. Wu; Viraphol Chaiyakul (ICCAD, 1992)

An efficient multi-view design model for real-time interactive synthesis. - Allen C.-H. Wu; Tedd Hadley; Daniel Gajski (ICCAD, 1992)

Benchmarking and the Art of Syntesis Tool Comparison. - Daniel Gajski; Nikil D. Dutt (Synthesis for Control Dominated Circuits, 1992)

System Level Specification and Synthesis. - Sanjiv Narayan; Frank Vahid; Daniel D. Gajski (VLSI Design, 1992)

System Specification with the SpecCharts Language. - Sanjiv Narayan; Frank Vahid; Daniel D. Gajski (IEEE Des. Test Comput., 1992)

Layout placement for sliced architecture. - Lawrence L. Larmore; Daniel D. Gajski; Allen C.-H. Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Partitioning algorithms for layout synthesis from register-transfer netlists. - Allen C.-H. Wu; Daniel D. Gajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

High-Level Transformations for Minimizing Syntactic Variances. - Viraphol Chaiyakul; Daniel Gajski; Loganath Ramachandran (DAC, 1993)

Top-down modeling of RISC processors in VHDL. - Hsiao-Ping Juan; Nancy D. Holmes; Smita Bakshi; Daniel D. Gajski (EURO-DAC, 1993)

Features supporting system-level specification in HDLs. - Sanjiv Narayan; Daniel D. Gajski (EURO-DAC, 1993)

Architectural tradeoffs in synthesis of pipelined controls. - Loganath Ramachandran; Daniel D. Gajski (EURO-DAC, 1993)

Synthesis of functions and procedures in behavioral VHDL. - Loganath Ramachandran; Sanjiv Narayan; Frank Vahid; Daniel D. Gajski (EURO-DAC, 1993)

Component synthesis from functional descriptions. - Elke A. Rundensteiner; Daniel D. Gajski; Lubomir Bic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Protocol Generation for Communication Channels. - Sanjiv Narayan; Daniel Gajski (DAC, 1994)

A component selection algorithm for high-performance pipelines. - Smita Bakshi; Daniel D. Gajski (EURO-DAC, 1994)

A System-Design Methodology: Executable-Specification Refinement. - Daniel Gajski; Frank Vahid; Sanjiv Narayan (EDAC-ETC-EUROASIC, 1994)

A performance evaluator for parameterized ASIC architectures. - Jie Gong; Daniel D. Gajski; Alex Nicolau (EURO-DAC, 1994)

An Algorithm for Generation of Behavioral Shape Functions. - Nancy D. Holmes; Daniel Gajski (EDAC-ETC-EUROASIC, 1994)

Synthesis of System-Level Bus Interfaces. - Sanjiv Narayan; Daniel Gajski (EDAC-ETC-EUROASIC, 1994)

An Algorithm for Array Variable Clustering. - Loganath Ramachandran; Daniel Gajski; Viraphol Chaiyakul (EDAC-ETC-EUROASIC, 1994)

100-hour design cycle: a test case. - Loganath Ramachandran; Daniel D. Gajski; Sanjiv Narayan; Frank Vahid; Peter Fung (EURO-DAC, 1994)

A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning. - Frank Vahid; Daniel D. Gajski; Jie Gong (EURO-DAC, 1994)

A transformation for integrating VHDL behavioral specification with synthesis and software generation. - Frank Vahid; Daniel D. Gajski; Sanjiv Narayan (EURO-DAC, 1994)

Design exploration for high-performance pipelines. - Smita Bakshi; Daniel D. Gajski (ICCAD, 1994)

Condition graphs for high-quality behavioral synthesis. - Hsiao-Ping Juan; Viraphol Chaiyakul; Daniel D. Gajski (ICCAD, 1994)

Introduction to High-Level Synthesis. - Daniel D. Gajski; Loganath Ramachandran (IEEE Des. Test Comput., 1994)

A transformation-based method for loop folding. - Tsing-Fa Lee; Allen C.-H. Wu; Youn-Long Lin; Daniel D. Gajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Interfacing Incompatible Protocols Using Interface Process Generation. - Sanjiv Narayan; Daniel Gajski (DAC, 1995)

Software estimation using a generic-processor model. - Jie Gong; Daniel D. Gajski; Sanjiv Narayan (ED&TC, 1995)

Architectural exploration for datapaths with memory hierarchy. - Nancy D. Holmes; Daniel D. Gajski (ED&TC, 1995)

SLIF: a specification-level intermediate format for system design. - Frank Vahid; Daniel D. Gajski (ED&TC, 1995)

A memory selection algorithm for high-performance pipelines. - Smita Bakshi; Daniel D. Gajski (EURO-DAC, 1995)

Closeness metrics for system-level functional partitioning. - Frank Vahid; Daniel D. Gajski (EURO-DAC, 1995)

Clustering for improved system-level functional partitioning. - Frank Vahid; Daniel D. Gajski (ISSS, 1995)

Specification and Design of Embedded Hardware-Software Systems. - Daniel D. Gajski; Frank Vahid (IEEE Des. Test Comput., 1995)

SpecCharts: a VHDL front-end for embedded systems. - Frank Vahid; Sanjiv Narayan; Daniel D. Gajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Performance evaluation for application-specific architectures. - Jie Gong; Daniel D. Gajski; Alexandru Nicolau (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Incremental hardware estimation during hardware/software functional partitioning. - Frank Vahid; Daniel D. Gajski (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Component selection in resource shared and pipelined DSP applications. - Smita Bakshi; Daniel D. Gajski; Hsiao-Ping Juan (EURO-DAC, 1996)

Clock optimization for high-performance pipelined design. - Hsiao-Ping Juan; Smita Bakshi; Daniel D. Gajski (EURO-DAC, 1996)

Rapid performance estimation for system design. - Sanjiv Narayan; Daniel D. Gajski (EURO-DAC, 1996)

Clock-driven performance optimization in interactive behavioral synthesis. - Hsiao-Ping Juan; Daniel Gajski; Viraphol Chaiyakul (ICCAD, 1996)

Opportunities and pitfalls in HDL-based system design. - Rajesh K. Gupta 001; Daniel Gajski; Randy Allen; Yatin Trivedi (ICCD, 1996)

An optimal clock period selection method based on slack minimization criteria. - En-Shou Chang; Daniel Gajski; Sanjiv Narayan (ACM Trans. Design Autom. Electr. Syst., 1996)

Component selection for high-performance pipelines. - Smita Bakshi; Daniel D. Gajski (IEEE Trans. Very Large Scale Integr. Syst., 1996)

System design methodologies: aiming at the 100 h design cycle. - Daniel D. Gajski; Sanjiv Narayan; Loganath Ramachandran; Frank Vahid; Peter Fung (IEEE Trans. Very Large Scale Integr. Syst., 1996)

A quantitative analysis for optimizing memory allocation. - Youn-Sik Hong; Choong-Hee Cho; Daniel D. Gajski (ASP-DAC, 1997)

Hardware/Software Partitioning and Pipelining. - Smita Bakshi; Daniel Gajski (DAC, 1997)

A Scheduling and Pipelining Algorithm for Hardware/Software Systems. - Smita Bakshi; Daniel Gajski (ISSS, 1997)

Model refinement for hardware-software codesign. - Jie Gong; Daniel Gajski; Smita Bakshi (ACM Trans. Design Autom. Electr. Syst., 1997)

System-level exploration with SpecSyn. - Daniel Gajski; Frank Vahid; Sanjiv Narayan; Jie Gong (DAC, 1998)

Hierarchical pipelining for behaviors, loops, and operations. - Smita Bakshi; Daniel D. Gajski (ICCD, 1998)

IP-Centric Methodology and Specification Language. - Daniel Gajski; Rainer Dömer; Jianwen Zhu (DIPES, 1998)

Specification and Design of Embedded Systems. - Rainer Dömer; Daniel D. Gajski; Jianwen Zhu (Informationstechnik Tech. Inform., 1998)

SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design. - Daniel D. Gajski; Frank Vahid; Sanjiv Narayan; Jie Gong (IEEE Trans. Very Large Scale Integr. Syst., 1998)

A unified formal model of ISA and FSMD. - Jianwen Zhu; Daniel Gajski (CODES, 1999)

IP-based Design Methodology. - Daniel Gajski (DAC, 1999)

Soft Scheduling in High Level Synthesis. - Jianwen Zhu; Daniel Gajski (DAC, 1999)

OpenJ: An Extensible System Level Design Language. - Jianwen Zhu; Daniel Gajski (DATE, 1999)

Rapid Prototyping with HW/SW Codesign Tool. - Dai Araki; Tadatoshi Ishii; Daniel Gajski (ECBS, 1999)

Panel Statement: System-Level Design: Designers' Wish List vs. Reality. - Daniel Gajski; Reinaldo A. Bergamaschi (ISSS, 1999)

Partitioning and pipelining for performance-constrained hardware/software systems. - Smita Bakshi; Daniel D. Gajski (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Reuse and protection of intellectual property in the SpecC system. - Rainer Dömer; Daniel Gajski (ASP-DAC, 2000)

Usage-based characterization of complex functional blocks for reuse in behavioral synthesis. - Nong Fan; Viraphol Chaiyakul; Daniel Gajski (ASP-DAC, 2000)

Embedded tutorial: essential issues for IP reuse. - Daniel Gajski; Allen C.-H. Wu; Viraphol Chaiyakul; Shojiro Mori; Tom Nukiyama; Pierre Bricaud (ASP-DAC, 2000)

One language or more?: how can we design an SoC at a system level? - Masaharu Imai; Gary Smith 001; Steven Schulz; Karen Bartleson; Daniel Gajski; Wolfgang Rosenstiel; Peter Flake; Hiroto Yasuura (ASP-DAC, 2000)

The Specification Language SpecC within the PARADISE Design Environment. - Achim Rettberg; Franz J. Rammig; Andreas Gerstlauer; Daniel Gajski; Wolfram Hardt; Bernd Kleinjohann (DIPES, 2000)

System Design - A Practical Guide with SpecC. - Andreas Gerstlauer; Rainer Dömer; Junyu Peng; Daniel D. Gajski (Springer, 2001)

Compiling SpecC for simulation. - Jianwen Zhu; Daniel Gajski (ASP-DAC, 2001)

Panel: The Next HDL: If C++ is the Answer, What was the Question? - Rajesh K. Gupta 001; Shishpal Rawat; Ingrid Verbauwhede; Gérard Berry; Ramesh Chandra; Daniel Gajski; Kris Konigsfeld; Patrick Schaumont (DAC, 2001)

C/C++: progress or deadlock in system-level specification. - Daniel Gajski; Eugenio Villar; Wolfgang Rosenstiel; Vassilios Gerousis; D. Barton; Jonas Plantin; S. E. Ericsson; Patrizia Cavalloro; Gjalt G. de Jong (DATE, 2001)

Introduction of system level architecture exploration using the SpecC methodology. - Lukai Cai; Daniel Gajski; Mike Olivarez (ISCAS (5), 2001)

RTL semantics and methodology. - Brian Bailey; Daniel Gajski (ISSS, 2001)

Performance-constrained hierarchical pipelining for behaviors, loops, and operations. - Smita Bakshi; Daniel Gajski (ACM Trans. Design Autom. Electr. Syst., 2001)

Co-design of embedded controllers for power electronics and electric systems. - Slim Ben Saoud; Daniel D. Gajski; Andreas Gerstlauer (ISIC, 2002)

Top-Down System Level Design Methodology Using SpecC, VCC and SystemC. - Lukai Cai; Daniel Gajski; Paul Kritzinger; Mike Olivarez (DATE, 2002)

Modeling a new RTL semantics in C++. - Shuqing Zhao; Daniel Gajski (ISCAS (5), 2002)

System-Level Abstraction Semantics. - Daniel Gajski; Andreas Gerstlauer (ISSS, 2002)

Optimal Message-Passing for Data Coherency in Distributed Architecture. - Daniel Gajski; Junyu Peng (ISSS, 2002)

Seamless approach for the design of control systems for power electronics and electric drives. - Slim Ben Saoud; Daniel D. Gajski; Andreas Gerstlauer (SMC, 2002)

Automatic Model Refinement for Fast Architecture Exploration. - Junyu Peng; Samar Abdi; Daniel Gajski (ASP-DAC/VLSI Design, 2002)

An ultra-fast instruction set simulator. - Jianwen Zhu; Daniel D. Gajski (IEEE Trans. Very Large Scale Integr. Syst., 2002)

RTOS Modeling for System Level Design. - Andreas Gerstlauer; Haobo Yu; Daniel D. Gajski (Embedded Software for SoC, 2003)

Transaction level modeling: an overview. - Lukai Cai; Daniel Gajski (CODES+ISSS, 2003)

RTOS scheduling in transaction level models. - Haobo Yu; Andreas Gerstlauer; Daniel Gajski (CODES+ISSS, 2003)

Automatic communication refinement for system level design. - Samar Abdi; Dongwan Shin; Daniel Gajski (DAC, 2003)

RTOS Modeling for System Level Design. - Andreas Gerstlauer; Haobo Yu; Daniel Gajski (DATE, 2003)

Transaction Based Design: Another Buzzword or the Solution to a Design Problem? - Heinz-Josef Schlebusch; Gary Smith 001; Donatella Sciuto; Daniel Gajski; Carsten Mielenz; Christopher K. Lennard; Frank Ghenassia; Stuart Swan; Joachim Kunkel (DATE, 2003)

On deriving equivalent architecture model from system specification. - Samar Abdi; Daniel Gajski (ASP-DAC, 2004)

A novel memory size model for variable-mapping in system level design. - Lukai Cai; Haobo Yu; Daniel Gajski (ASP-DAC, 2004)

Automatic generation of bus functional models from transaction level models. - Dongwan Shin; Samar Abdi; Daniel Gajski (ASP-DAC, 2004)

Embedded software generation from system level design languages. - Haobo Yu; Rainer Dömer; Daniel Gajski (ASP-DAC, 2004)

Embedded systems education: how to teach the required skills? - Peter Marwedel; Daniel Gajski; Erwin A. de Kock; Hugo De Man; Mariagiovanna Sami; Ingemar Söderquist (CODES+ISSS, 2004)

Automatic generation of equivalent architecture model from functional specification. - Samar Abdi; Daniel Gajski (DAC, 2004)

Retargetable profiling for rapid, early system-level design space exploration. - Lukai Cai; Andreas Gerstlauer; Daniel Gajski (DAC, 2004)

Were the good old days all that good?: EDA then and now. - Shishpal Rawat; William H. Joyner Jr.; John A. Darringer; Daniel Gajski; Pat O. Pistilli; Hugo De Man; Carl Harris; James Solomon (DAC, 2004)

Model validation for mapping specification behaviors to processing elements. - Samar Abdi; Daniel Gajski (HLDVT, 2004)

A formalism for functionality preserving system level transformations. - Samar Abdi; Daniel Gajski (ASP-DAC, 2005)

Multi-metric and multi-entity characterization of applications for early system design exploration. - Lukai Cai; Andreas Gerstlauer; Daniel Gajski (ASP-DAC, 2005)

System-level communication modeling for network-on-chip synthesis. - Andreas Gerstlauer; Dongwan Shin; Rainer Dömer; Daniel D. Gajski (ASP-DAC, 2005)

A clustering technique to optimize hardware/software synchronization. - Junyu Peng; Samar Abdi; Daniel Gajski (ASP-DAC, 2005)

What will system level design be when it grows up? - Grant Martin; Daniel Gajski; David Goodwin; Patrick Lysaght; Peter Marwedel; Mike Muller; Jeff Welser (CODES+ISSS, 2005)

A cycle-accurate compilation algorithm for custom pipelined datapaths. - Mehrdad Reshadi; Daniel Gajski (CODES+ISSS, 2005)

Automatic network generation for system-on-chip communication design. - Dongwan Shin; Andreas Gerstlauer; Rainer Dömer; Daniel D. Gajski (CODES+ISSS, 2005)

Functional Validation of System Level Static Scheduling. - Samar Abdi; Daniel D. Gajski (DATE, 2005)

Defining an Enhanced RTL Semantics. - Shuqing Zhao; Daniel D. Gajski (DATE, 2005)

Custom Processor Design Using NISC: A Case-Study on DCT algorithm. - Bita Gorjiara; Daniel D. Gajski (ESTIMedia, 2005)

Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths. - Mehrdad Reshadi; Bita Gorjiara; Daniel D. Gajski (ICCD, 2005)

Automatic Generation of Communication Architectures. - Dongwan Shin; Andreas Gerstlauer; Rainer Dömer; Daniel D. Gajski (IESS, 2005)

Software and Driver Synthesis from Transaction Level Models. - Haobo Yu; Rainer Dömer; Daniel D. Gajski (IESS, 2005)

System design extreme makeover. - Daniel Gajski (MEMOCODE, 2005)

Structural operational semantics for supporting multi-cycle operations in RTL HDLs. - Shuqing Zhao; Daniel D. Gajski (MEMOCODE, 2005)

Design and implementation of transducer for ARM-TMS communication. - Hansu Cho; Samar Abdi; Daniel Gajski (ASP-DAC, 2006)

Designing a custom architecture for DCT using NISC technology. - Bita Gorjiara; Mehrdad Reshadi; Daniel D. Gajski (ASP-DAC, 2006)

Generic netlist representation for system and PE level design exploration. - Bita Gorjiara; Mehrdad Reshadi; Pramod Chandraiah; Daniel Gajski (CODES+ISSS, 2006)

Automatic generation of transaction level models for rapid design space exploration. - Dongwan Shin; Andreas Gerstlauer; Junyu Peng; Rainer Dömer; Daniel D. Gajski (CODES+ISSS, 2006)

A Graph Based Algorithm for Data Path Optimization in Custom Processors. - Jelena Trajkovic; Mehrdad Reshadi; Bita Gorjiara; Daniel Gajski (DSD, 2006)

Transaction Routing and its Verification by Correct Model Transformations. - Samar Abdi; Daniel Gajski (HLDVT, 2006)

Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths . - Bita Gorjiara; Mehrdad Reshadi; Daniel Gajski (ICCD, 2006)

Verification of System Level Model Transformations. - Samar Abdi; Daniel Gajski (Int. J. Parallel Program., 2006)

TLM: Crossing Over From Buzz To Adoption. - Francine Bacchini; Daniel D. Gajski; Laurent Maillet-Contoz; Haruhisa Kashiwagi; Jack Donovan; Tommi Mäkeläinen; Jack Greenbaum; Rishiyur S. Nikhil (DAC, 2007)

Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems. - Mehrdad Reshadi; Daniel Gajski (DATE, 2007)

New Strategies for System-Level Design. - Daniel D. Gajski (DDECS, 2007)

FPGA-friendly code compression for horizontal microcoded custom IPs. - Bita Gorjiara; Daniel Gajski (FPGA, 2007)

A novel profile-driven technique for simultaneous power and code-size optimization of microcoded IPs. - Bita Gorjiara; Daniel Gajski (ICCD, 2007)

An Interactive Design Environment for C-based High-Level Synthesis. - Dongwan Shin; Andreas Gerstlauer; Rainer Dömer; Daniel D. Gajski (IESS, 2007)

Automatic Data Path Generation from C code for Custom Processors. - Jelena Trajkovic; Daniel Gajski (IESS, 2007)

Interface synthesis for heterogeneous multi-core systems from transaction level models. - Hansu Cho; Samar Abdi; Daniel Gajski (LCTES, 2007)

Automatic generation of embedded communication SW for heterogeneous MPSoC platforms. - Ines Viskic; Samar Abdi; Daniel D. Gajski (LCTES, 2007)

Automatic Layer-Based Generation of System-On-Chip Bus Communication Models. - Andreas Gerstlauer; Dongwan Shin; Junyu Peng; Rainer Dömer; Daniel Gajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Specify-explore-refine (SER): from specification to implementation. - Andreas Gerstlauer; Junyu Peng; Dongwan Shin; Daniel Gajski; Atsushi Nakamura; Dai Araki; Yuuji Nishihara (DAC, 2008)

Automatic architecture refinement techniques for customizing processing elements. - Bita Gorjiara; Daniel Gajski (DAC, 2008)

C-based design flow: a case study on G.729A for voice over internet protocol (VoIP). - Mehrdad Reshadi; Bita Gorjiara; Daniel Gajski (DAC, 2008)

Cycle-approximate Retargetable Performance Estimation at the Transaction Level. - Yonghyun Hwang; Samar Abdi; Daniel Gajski (DATE, 2008)

Custom Processor Core Construction from C Code. - Jelena Trajkovic; Daniel D. Gajski (SASP, 2008)

System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design. - Rainer Dömer; Andreas Gerstlauer; Junyu Peng; Dongwan Shin; Lukai Cai; Haobo Yu; Samar Abdi; Daniel D. Gajski (EURASIP J. Embed. Syst., 2008)

Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs. - Bita Gorjiara; Mehrdad Reshadi; Daniel Gajski (ACM Trans. Reconfigurable Technol. Syst., 2008)

An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors. - Dongwan Shin; Andreas Gerstlauer; Rainer Dömer; Daniel Gajski (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Hardware-dependent software synthesis for many-core embedded systems. - Samar Abdi; Gunar Schirner; Ines Viskic; Hansu Cho; Yonghyun Hwang; Lochi Yu; Daniel Gajski (ASP-DAC, 2009)

An Introduction to High-Level Synthesis. - Philippe Coussy; Daniel D. Gajski; Michael Meredith; Andrés Takach (IEEE Des. Test Comput., 2009)

Model Based Synthesis of Embedded Software. - Samar Abdi; Daniel Gajski; Ines Viskic (J. Softw., 2009)

Electronic System-Level Synthesis Methodologies. - Andreas Gerstlauer; Christian Haubelt; Andy D. Pimentel; Todor P. Stefanov; Daniel D. Gajski; Jürgen Teich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

What input-language is the best choice for high level synthesis (HLS)? - Daniel Gajski; Todd M. Austin; Steve Svoboda (DAC, 2010)

Accurate timed RTOS model for transaction level modeling. - Yonghyun Hwang; Gunar Schirner; Samar Abdi; Daniel D. Gajski (DATE, 2010)

Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications. - Ines Viskic; Lochi Yu; Daniel Gajski (LCTES, 2010)

Embedded system environment: A framework for TLM-based design and prototyping. - Samar Abdi; Yonghyun Hwang; Lochi Yu; Hansu Cho; Ines Viskic; Daniel D. Gajski (International Symposium on Rapid System Prototyping, 2010)

Early performance-cost estimation of application-specific data path pipelining. - Jelena Trajkovic; Daniel D. Gajski (SASP, 2010)

Automatic TLM Generation for Early Validation of Multicore Systems. - Samar Abdi; Yonghyun Hwang; Lochi Yu; Gunar Schirner; Daniel D. Gajski (IEEE Des. Test Comput., 2011)

Automated Generation of Custom Processor Core from C Code. - Jelena Trajkovic; Samar Abdi; Gabriela Nicolescu; Daniel D. Gajski (J. Electr. Comput. Eng., 2012)

Trace-Driven Performance Estimation of multi-core platforms. - Kyoungwon Kim; Daniel D. Gajski (MWSCAS, 2014)

Hierarchy-Aware mapping of pipelined applications. - Kyoungwon Kim; Daniel D. Gajski (MWSCAS, 2014)

Implementing flexible hybrid instruction in an electrical engineering course: The best of three worlds? - Wenliang He; Daniel Gajski; George Farkas; Mark Warschauer (Comput. Educ., 2015)

A case study to develop a graduate-level degree program in embedded & cyber-physical systems. - Fadi J. Kurdahi; Mohammad Abdullah Al Faruque; Daniel Gajski; Ahmed M. Eltawil (SIGBED Rev., 2016)