Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics. - Frank Schmiedle; Daniel Große; Rolf Drechsler; Bernd Becker 001 (Fuzzy Days, 2001)

Reachability Analysis for Formal Verification of SystemC. - Rolf Drechsler; Daniel Große (DSD, 2002)

Heuristic Learning Based on Genetic Programming. - Frank Schmiedle; Nicole Drechsler; Daniel Große; Rolf Drechsler (Genet. Program. Evolvable Mach., 2002)

Efficient Automatic Visualization of SystemC Designs. - Daniel Große; Rolf Drechsler; Lothar Linhard; Gerhard Angst (FDL, 2003)

BDD-based verification of scalable designs. - Daniel Große; Rolf Drechsler (HLDVT, 2003)

Formal verification of LTL formulas for SystemC designs. - Daniel Große; Rolf Drechsler (ISCAS (5), 2003)

Modeling Multi-Valued Circuits in SystemC. - Daniel Große; Görschwin Fey; Rolf Drechsler (ISMVL, 2003)

Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen. - Daniel Große; Rolf Drechsler (MBMV, 2003)

Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC. - Daniel Große; Rolf Drechsler (it Inf. Technol., 2003)

Checkers for SystemC designs. - Daniel Große; Rolf Drechsler (MEMOCODE, 2004)

Acceleration of SAT-Based Iterative Property Checking. - Daniel Große; Rolf Drechsler (CHARME, 2005)

Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors. - Daniel Große; Ulrich Kühne; Rolf Drechsler (GI Jahrestagung (1), 2005)

CheckSyC: an efficient property checker for RTL SystemC designs. - Daniel Große; Rolf Drechsler (ISCAS (4), 2005)

HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. - Daniel Große; Ulrich Kühne; Rolf Drechsler (MTV, 2005)

SyCE: An Integrated Environment for System Design in SystemC. - Rolf Drechsler; Görschwin Fey; Christian Genz; Daniel Große (IEEE International Workshop on Rapid System Prototyping, 2005)

Avoiding false negatives in formal verification for protocol-driven blocks. - Görschwin Fey; Daniel Große; Rolf Drechsler (DATE, 2006)

HW/SW co-verification of embedded systems using bounded model checking. - Daniel Große; Ulrich Kühne; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2006)

Estimating functional coverage in bounded model checking. - Daniel Große; Ulrich Kühne; Rolf Drechsler (DATE, 2007)

Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques. - Daniel Große; Hernan Peraza; Wolfgang Klingauf; Rolf Drechsler (FDL, 2007)

Exact sat-based toffoli network synthesis. - Daniel Große; Xiaobo Chen; Gerhard W. Dueck; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2007)

Improvements for constraint solving in the systemc verification library. - Daniel Große; Rüdiger Ebendt; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2007)

Fast exact Toffoli network synthesis of reversible logic. - Robert Wille; Daniel Große (ICCAD, 2007)

Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. - Mahsan Amoui; Daniel Große; Mitchell A. Thornton; Rolf Drechsler (ISMVL, 2007)

Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. - Ulrich Kühne; Daniel Große; Rolf Drechsler (ISVLSI, 2007)

Formal Verification on the Word Level using SAT-like Proof Techniques. - Görschwin Fey; Daniel Große; Stephan Eggersglüß; Robert Wille; Rolf Drechsler (MBMV, 2007)

SWORD: A SAT like Prover Using Word Level Information. - Robert Wille; Görschwin Fey; Daniel Große; Stephan Eggersglüß; Rolf Drechsler (VLSI-SoC (Selected Papers), 2007)

Quantified Synthesis of Reversible Logic. - Robert Wille; Hoang Minh Le 001; Gerhard W. Dueck; Daniel Große (DATE, 2008)

Contradiction Analysis for Constraint-based Random Simulation. - Daniel Große; Robert Wille; Robert Siegmund; Rolf Drechsler (FDL, 2008)

Debugging Contradictory Constraints in Constraint-Based Random Simulation. - Daniel Große; Robert Wille; Robert Siegmund; Rolf Drechsler (FDL (Selected Papers), 2008)

Qualitätsorientierter Entwurfs- und Verifikationsablauf für digitale Systeme [Quality-Driven Design and Verification Flow for Digital Systems]. - Daniel Große (Ausgezeichnete Informatikdissertationen, 2008)

Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. - Daniel Große; Robert Wille; Gerhard W. Dueck; Rolf Drechsler (ISMVL, 2008)

RevLib: An Online Resource for Reversible Functions and Reversible Circuits. - Robert Wille; Daniel Große; Lisa Teuber; Gerhard W. Dueck; Rolf Drechsler (ISMVL, 2008)

Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. - Robert Wille; Daniel Große; Mathias Soeken; Rolf Drechsler (ISVLSI, 2008)

Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking. - Daniel Große; Robert Wille; Ulrich Kühne; Rolf Drechsler (MBMV, 2008)

Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow. - Ulrich Kühne; Daniel Große; Rolf Drechsler (MTV, 2008)

Analyzing Functional Coverage in Bounded Model Checking. - Daniel Große; Ulrich Kühne; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Formal Verification of Abstract SystemC Models. - Daniel Große; Hoang Minh Le 001; Rolf Drechsler (Algorithms and Applications for Next Generation SAT Solvers, 2009)

Property analysis and design understanding. - Ulrich Kühne; Daniel Große; Rolf Drechsler (DATE, 2009)

Debugging of Toffoli networks. - Robert Wille; Daniel Große; Stefan Frehse; Gerhard W. Dueck; Rolf Drechsler (DATE, 2009)

SMT-based stimuli generation in the SystemC Verification library. - Robert Wille; Daniel Große; Finn Haedicke; Rolf Drechsler (FDL, 2009)

Contradictory antecedent debugging in bounded model checking. - Daniel Große; Robert Wille; Ulrich Kühne; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2009)

Induction-Based Formal Verification of SystemC TLM Designs. - Daniel Große; Hoang Minh Le 001; Rolf Drechsler (MTV, 2009)

WoLFram- A Word Level Framework for Formal Verification. - André Sülflow; Ulrich Kühne; Görschwin Fey; Daniel Große; Rolf Drechsler (IEEE International Workshop on Rapid System Prototyping, 2009)

Reversible Logic Synthesis with Output Permutation. - Robert Wille; Daniel Große; Gerhard W. Dueck; Rolf Drechsler (VLSI Design, 2009)

Exact Synthesis of Elementary Quantum Gate Circuits. - Daniel Große; Robert Wille; Gerhard W. Dueck; Rolf Drechsler (J. Multiple Valued Log. Soft Comput., 2009)

Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. - Daniel Große; Robert Wille; Gerhard W. Dueck; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Quality-Driven SystemC Design - Daniel Große; Rolf Drechsler (Springer, 2010)

Towards analyzing functional coverage in SystemC TLM property checking. - Hoang Minh Le 001; Daniel Große; Rolf Drechsler (HLDVT, 2010)

Proving transaction and system-level properties of untimed SystemC TLM designs. - Daniel Große; Hoang Minh Le 001; Rolf Drechsler (MEMOCODE, 2010)

Automatic Fault Localization for SystemC TLM Designs. - Hoang Minh Le 001; Daniel Große; Rolf Drechsler (MTV, 2010)

Towards Fully Automatic Synthesis of Embedded Software. - Ulrich Kühne; Daniel Große; Rolf Drechsler (IEEE Embed. Syst. Lett., 2010)

TLM protocol compliance checking at the Electronic System Level. - Mohamed Bawadekji; Daniel Große; Rolf Drechsler (DDECS, 2011)

Analyzing dependability measures at the Electronic System Level. - Marc Michael; Daniel Große; Rolf Drechsler (FDL, 2011)

metaSMT: Focus on Your Application not on Solver Integration. - Finn Haedicke; Stefan Frehse; Görschwin Fey; Daniel Große; Rolf Drechsler (DIFTS@FMCAD, 2011)

Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines. - Kim Grüttner; Andreas Herrholz; Ulrich Kühne; Daniel Große; Achim Rettberg; Wolfgang Nebel; Rolf Drechsler (ISORC Workshops, 2011)

Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction. - Daniel Große; Markus Groß 002; Ulrich Kühne; Rolf Drechsler (MBMV, 2011)

Designing a RISC CPU in Reversible Logic. - Robert Wille; Mathias Soeken; Daniel Große; Eleonora Schönborn; Rolf Drechsler (MBMV, 2011)

Debugging reversible circuits. - Robert Wille; Daniel Große; Stefan Frehse; Gerhard W. Dueck; Rolf Drechsler (Integr., 2011)

The system verification methodology for advanced TLM verification. - Marcio Ferreira da Silva Oliveira; Christoph Kuznik; Hoang Minh Le 001; Daniel Große; Finn Haedicke; Wolfgang Müller 003; Rolf Drechsler; Wolfgang Ecker; Volkan Esen (CODES+ISSS, 2012)

A guiding coverage metric for formal verification. - Finn Haedicke; Daniel Große; Rolf Drechsler (DATE, 2012)

Coverage-Driven Stimuli Generation. - Shuo Yang 009; Robert Wille; Daniel Große; Rolf Drechsler (DSD, 2012)

Localizing features of ESL models for design understanding. - Marc Michael; Daniel Große; Rolf Drechsler (FDL, 2012)

Completeness-Driven Development. - Rolf Drechsler; Melanie Diepenbeck; Daniel Große; Ulrich Kühne; Hoang Minh Le 001; Julia Seiter 002; Mathias Soeken; Robert Wille (ICGT, 2012)

Behavior Driven Development for circuit design and verification. - Melanie Diepenbeck; Mathias Soeken; Daniel Große; Rolf Drechsler (HLDVT, 2012)

From Requirements and Scenarios to ESL Design in SystemC. - Hoang M. Le; Daniel Große; Rolf Drechsler (ISED, 2012)

CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC. - Finn Haedicke; Hoang Minh Le 001; Daniel Große; Rolf Drechsler (MBMV, 2012)

Equivalence Checking of Reversible Circuits. - Robert Wille; Daniel Große; D. Michael Miller; Rolf Drechsler (J. Multiple Valued Log. Soft Comput., 2012)

Automatic TLM Fault Localization for SystemC. - Hoang Minh Le 001; Daniel Große; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Verifying SystemC using an intermediate verification language and symbolic simulation. - Hoang Minh Le 001; Daniel Große; Vladimir Herdt; Rolf Drechsler (DAC, 2013)

Scalable fault localization for SystemC TLM designs. - Hoang Minh Le 001; Daniel Große; Rolf Drechsler (DATE, 2013)

Minimal Stimuli Generation in Simulation-Based Verification. - Shuo Yang 009; Robert Wille; Daniel Große; Rolf Drechsler (DSD, 2013)

Towards automatic scenario generation from coverage information. - Melanie Diepenbeck; Mathias Soeken; Daniel Große; Rolf Drechsler (AST, 2013)

Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis. - Daniel Große; Görschwin Fey; Rolf Drechsler (Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2013)

Constraint-based platform variants specification for early system verification. - Andreas Burger; Alexander Viehl; Andreas Braun; Finn Haedicke; Daniel Große; Oliver Bringmann 001; Wolfgang Rosenstiel (ASP-DAC, 2014)

Funktionale Abdeckungsanalyse von C-Programmen. - Aljoscha Windhorst; Hoang Minh Le 001; Daniel Große; Rolf Drechsler (MBMV, 2014)

Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules. - Vladimir Herdt; Hoang Minh Le 001; Daniel Große; Rolf Drechsler (ATVA, 2015)

Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits. - Amr A. R. Sayed-Ahmed; Ulrich Kühne; Daniel Große; Rolf Drechsler (ISVLSI, 2015)

BDD minimization for approximate computing. - Mathias Soeken; Daniel Große; Arun Chandrasekharan; Rolf Drechsler (ASP-DAC, 2016)

ParCoSS: Efficient Parallelized Compiled Symbolic Simulation. - Vladimir Herdt; Hoang Minh Le 001; Daniel Große; Rolf Drechsler (CAV (2), 2016)

Precise error determination of approximated components in sequential circuits with model checking. - Arun Chandrasekharan; Mathias Soeken; Daniel Große; Rolf Drechsler (DAC, 2016)

Quantitative timing analysis of UML activity diagrams using statistical model checking. - Fan Gu; Xinqian Zhang; Mingsong Chen 001; Daniel Große; Rolf Drechsler (DATE, 2016)

Towards formal verification of real-world SystemC TLM peripheral models - a case study. - Hoang Minh Le 001; Vladimir Herdt; Daniel Große; Rolf Drechsler (DATE, 2016)

Formal verification of integer multipliers by combining Gröbner basis with logic reduction. - Amr A. R. Sayed-Ahmed; Daniel Große; Ulrich Kühne; Mathias Soeken; Rolf Drechsler (DATE, 2016)

On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. - Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (FDL, 2016)

Equivalence checking using Gröbner bases. - Amr A. R. Sayed-Ahmed; Daniel Große; Mathias Soeken; Rolf Drechsler (FMCAD, 2016)

Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm. - Saeideh Shirinzadeh; Mathias Soeken; Daniel Große; Rolf Drechsler (GECCO (Companion), 2016)

Approximation-aware rewriting of AIGs for error tolerant applications. - Arun Chandrasekharan; Mathias Soeken; Daniel Große; Rolf Drechsler (ICCAD, 2016)

Compiled symbolic simulation for systemC. - Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (ICCAD, 2016)

Guided lightweight Software test qualification for IP integration using Virtual Prototypes. - Daniel Große; Hoang M. Le; Muhammad Hassan 002; Rolf Drechsler (ICCD, 2016)

Symbolic Error Metric Determination for Approximate Computing. - Arun Chandrasekharan; Daniel Große; Mathias Soeken; Rolf Drechsler (MBMV, 2016)

Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs. - Kenneth Schmitz; Arun Chandrasekharan; Jonas Gomes Filho; Daniel Große; Rolf Drechsler (ASP-DAC, 2017)

Data flow testing for virtual prototypes. - Muhammad Hassan 002; Vladimir Herdt; Hoang M. Le; Mingsong Chen 001; Daniel Große; Rolf Drechsler (DATE, 2017)

Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach. - Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (FDL (Selected Papers), 2017)

Semi-formal Cycle-Accurate Temporal Execution Traces Reconstruction. - Rehab Massoud; Jannis Stoppe; Daniel Große; Rolf Drechsler (FORMATS, 2017)

An adaptive prioritized ε-preferred evolutionary algorithm for approximate BDD optimization. - Saeideh Shirinzadeh; Mathias Soeken; Daniel Große; Rolf Drechsler (GECCO, 2017)

ProACt: A Processor for High Performance On-demand Approximate Computing. - Arun Chandrasekharan; Daniel Große; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2017)

Early SoC security validation by VP-based static information flow analysis. - Muhammad Hassan 002; Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (ICCAD, 2017)

Error Bounded Exact BDD Minimization in Approximate Computing. - Saman Fröhlich; Daniel Große; Rolf Drechsler (ISMVL, 2017)

Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing. - Saman Fröhlich; Daniel Große; Rolf Drechsler (MBMV, 2017)

Yise - a novel framework for boolean networks using y-inverter graphs. - Arun Chandrasekharan; Daniel Große; Rolf Drechsler (MEMOCODE, 2017)

metaSMT: focus on your application and not on solver integration. - Heinz Riener; Finn Haedicke; Stefan Frehse; Mathias Soeken; Daniel Große; Rolf Drechsler; Görschwin Fey (Int. J. Softw. Tools Technol. Transf., 2017)

Approximation-aware testing for approximate circuits. - Arun Chandrasekharan; Stephan Eggersglüß; Daniel Große; Rolf Drechsler (ASP-DAC, 2018)

Approximate hardware generation using symbolic computer algebra employing grobner basis. - Saman Fröhlich; Daniel Große; Rolf Drechsler (DATE, 2018)

Testbench qualification for SystemC-AMS timed data flow models. - Muhammad Hassan 002; Daniel Große; Hoang M. Le; Thilo Vörtler; Karsten Einwich; Rolf Drechsler (DATE, 2018)

Towards fully automated TLM-to-RTL property refinement. - Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (DATE, 2018)

Resilience evaluation via symbolic fault injection on intermediate code. - Hoang M. Le; Vladimir Herdt; Daniel Große; Rolf Drechsler (DATE, 2018)

An exact method for design exploration of quantum-dot cellular automata. - Marcel Walter; Robert Wille; Daniel Große; Frank Sill Torres; Rolf Drechsler (DATE, 2018)

Natural Language Based Power Domain Partitioning. - David Lemma; Daniel Große; Rolf Drechsler (DDECS, 2018)

Towards Reversed Approximate Hardware Design. - Saman Fröhlich; Daniel Große; Rolf Drechsler (DSD, 2018)

Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata. - Frank Sill Torres; Robert Wille; Marcel Walter; Philipp Niemann 001; Daniel Große; Rolf Drechsler (DSD, 2018)

Extensible and Configurable RISC-V Based Virtual Prototype. - Vladimir Herdt; Daniel Große; Hoang M. Le; Rolf Drechsler (FDL, 2018)

SAT-Lancer: A Hardware SAT-Solver for Self-Verification. - Buse Ustaoglu; Sebastian Huhn 001; Daniel Große; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2018)

PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers. - Alireza Mahzoon; Daniel Große; Rolf Drechsler (ICCAD, 2018)

Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers. - Alireza Mahzoon; Daniel Große; Rolf Drechsler (ISVLSI, 2018)

Towards Dynamic Execution Environment for System Security Protection Against Hardware Flaws. - Kenneth Schmitz; Oliver Keszöcze; Jurij Schmidt; Daniel Große; Rolf Drechsler (ISVLSI, 2018)

Towards Automated Refinement of TLM Properties to RTL. - Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (MBMV, 2018)

Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters*. - David Lemma; Mehran Goli; Daniel Große; Rolf Drechsler (NORCAS, 2018)

Behaviour Driven Development for Hardware Design. - Melanie Diepenbeck; Ulrich Kühne; Mathias Soeken; Daniel Große; Rolf Drechsler (IPSJ Trans. Syst. LSI Des. Methodol., 2018)

Approximate Hardware Generation Using Formal Techniques. - Saman Fröhlich; Daniel Große; Rolf Drechsler (Approximate Circuits, 2019)

(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs. - Kenneth Schmitz; Buse Ustaoglu; Daniel Große; Rolf Drechsler (ARC, 2019)

Maximizing power state cross coverage in firmware-based power management. - Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (ASP-DAC, 2019)

Scalable design for field-coupled nanocomputing circuits. - Marcel Walter; Robert Wille; Frank Sill Torres; Daniel Große; Rolf Drechsler (ASP-DAC, 2019)

Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning Systems. - Rolf Drechsler; Daniel Große (ATS, 2019)

Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study. - Vladimir Herdt; Daniel Große; Hoang M. Le; Rolf Drechsler (DAC, 2019)

RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers. - Alireza Mahzoon; Daniel Große; Rolf Drechsler (DAC, 2019)

One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing. - Saman Fröhlich; Daniel Große; Rolf Drechsler (DATE, 2019)

Data Flow Testing for SystemC-AMS Timed Data Flow Models. - Muhammad Hassan 002; Daniel Große; Hoang M. Le; Rolf Drechsler (DATE, 2019)

Verifying Instruction Set Simulators using Coverage-guided Fuzzing*. - Vladimir Herdt; Daniel Große; Hoang M. Le; Rolf Drechsler (DATE, 2019)

Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing. - Hoang M. Le; Daniel Große; Niklas Bruns; Rolf Drechsler (DATE, 2019)

Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents. - Tim Meywerk; Marcel Walter; Vladimir Herdt; Daniel Große; Rolf Drechsler (DSD, 2019)

SAT-Hard: A Learning-Based Hardware SAT-Solver. - Buse Ustaoglu; Sebastian Huhn 001; Frank Sill Torres; Daniel Große; Rolf Drechsler (DSD, 2019)

Functional Coverage-Driven Characterization of RF Amplifiers. - Muhammad Hassan 002; Daniel Große; Thilo Vörtler; Karsten Einwich; Rolf Drechsler (FDL, 2019)

Systematic RISC-V based Firmware Design⋆. - Vladimir Herdt; Daniel Große; Rolf Drechsler; Christoph Gerum; Alexander Jung; Joscha Benz; Oliver Bringmann 001; Michael Schwarz 010; Dominik Stoffel; Wolfgang Kunz (FDL, 2019)

Automated Analysis of Virtual Prototypes at Electronic System Level. - Mehran Goli; Muhammad Hassan 002; Daniel Große; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2019)

Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies. - Robert Wille; Marcel Walter; Frank Sill Torres; Daniel Große; Rolf Drechsler (ISVLSI, 2019)

fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits. - Marcel Walter; Robert Wille; Frank Sill Torres; Daniel Große; Rolf Drechsler (CoRR, 2019)

Security validation of VP-based SoCs using dynamic information flow tracking. - Mehran Goli; Muhammad Hassan 002; Daniel Große; Rolf Drechsler (it Inf. Technol., 2019)

Placement and Routing for Tile-based Field-coupled Nanocomputing Circuits Is NP-complete (Research Note). - Marcel Walter; Robert Wille; Daniel Große; Frank Sill Torres; Rolf Drechsler (ACM J. Emerg. Technol. Comput. Syst., 2019)

Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction. - Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (Int. J. Softw. Tools Technol. Transf., 2019)

Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation. - Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms. - Vladimir Herdt; Daniel Große; Rolf Drechsler (ATVA, 2020)

Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side*. - Vladimir Herdt; Daniel Große; Rolf Drechsler (DAC, 2020)

Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes. - Pascal Pieper; Vladimir Herdt; Daniel Große; Rolf Drechsler (DAC, 2020)

Verification for Field-coupled Nanocomputing Circuits. - Marcel Walter; Robert Wille; Frank Sill Torres; Daniel Große; Rolf Drechsler (DAC, 2020)

Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes*. - Vladimir Herdt; Daniel Große; Rolf Drechsler (DATE, 2020)

Towards Specification and Testing of RISC-V ISA Compliance⋆. - Vladimir Herdt; Daniel Große; Rolf Drechsler (DATE, 2020)

Towards Formal Verification of Optimized and Industrial Multipliers. - Alireza Mahzoon; Daniel Große; Christoph Scholl 001; Rolf Drechsler (DATE, 2020)

Towards Generation of a Programmable Power Management Unit at the Electronic System Level. - David Lemma; Mehran Goli; Daniel Große; Rolf Drechsler (DDECS, 2020)

Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study. - Vladimir Herdt; Daniel Große; Eyck Jentzsch; Rolf Drechsler (FDL, 2020)

Early Verification of ISA Extension Specifications using Deep Reinforcement Learning. - Niklas Bruns; Daniel Große; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2020)

Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes. - Vladimir Herdt; Daniel Große; Jonas Wloka; Tim Güneysu; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2020)

Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime. - Vladimir Herdt; Daniel Große; Sören Tempel; Rolf Drechsler (ICCD, 2020)

Clustering-Guided SMT($ mathcal {L !R !A}$) Learning. - Tim Meywerk; Marcel Walter; Daniel Große; Rolf Drechsler (IFM, 2020)

ASNet: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks. - Saman Fröhlich; Lucas Klemmer; Daniel Große; Rolf Drechsler (ISMVL, 2020)

Verifying Safety Properties of Robotic Plans Operating in Real-World Environments via Logic-Based Environment Modeling. - Tim Meywerk; Marcel Walter; Vladimir Herdt; Jan Kleinekathöfer; Daniel Große; Rolf Drechsler (ISoLA (3), 2020)

RISC-V based virtual prototype: An extensible and configurable platform for the system-level. - Vladimir Herdt; Daniel Große; Pascal Pieper; Rolf Drechsler (J. Syst. Archit., 2020)

On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata. - Frank Sill Torres; Pedro Arthur Silva; Geraldo Fontes; Marcel Walter; José Augusto Miranda Nacif; Ricardo Santos Ferreira 001; Omar Paranaiba Vilela Neto; Jeferson F. Chaves; Robert Wille; Philipp Niemann 001; Daniel Große; Rolf Drechsler (Microprocess. Microsystems, 2020)

System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations. - Muhammad Hassan 002; Daniel Große; Rolf Drechsler (ASP-DAC, 2021)

Mutation-based Compliance Testing for RISC-V. - Vladimir Herdt; Sören Tempel; Daniel Große; Rolf Drechsler (ASP-DAC, 2021)

System Level Verification of Phase-Locked Loop using Metamorphic Relations. - Muhammad Hassan 002; Daniel Große; Rolf Drechsler (DATE, 2021)

Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization. - Christoph Scholl 001; Alexander Konrad; Alireza Mahzoon; Daniel Große; Rolf Drechsler (DATE, 2021)

EPEX: Processor Verification by Equivalent Program Execution. - Lucas Klemmer; Daniel Große (ACM Great Lakes Symposium on VLSI, 2021)

XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding. - Lucas Klemmer; Saman Fröhlich; Rolf Drechsler; Daniel Große (ISCAS, 2021)

Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level. - Frank Riese; Vladimir Herdt; Daniel Große; Rolf Drechsler (VLSI-SoC, 2021)

Toward RISC-V CSR Compliance Testing. - Niklas Bruns; Vladimir Herdt; Daniel Große; Rolf Drechsler (IEEE Embed. Syst. Lett., 2021)

Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform. - Vladimir Herdt; Daniel Große; Sören Tempel; Rolf Drechsler (J. Syst. Archit., 2021)

WAL: A Novel Waveform Analysis Language for Advanced Design Understanding and Debugging. - Lucas Klemmer; Daniel Große (ASP-DAC, 2022)

Waveform-based performance analysis of RISC-V processors: late breaking results. - Lucas Klemmer; Daniel Große (DAC, 2022)

Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability. - Alireza Mahzoon; Daniel Große; Christoph Scholl 001; Alexander Konrad; Rolf Drechsler (DAC, 2022)

Verifying SystemC TLM peripherals using modern C++ symbolic execution tools. - Pascal Pieper; Vladimir Herdt; Daniel Große; Rolf Drechsler (DAC, 2022)

SpinalFuzz: Coverage-Guided Fuzzing for SpinalHDL Designs. - Katharina Ruep; Daniel Große (ETS, 2022)

Formal Verification of SUBLEQ Microcode implementing the RV32I ISA. - Lucas Klemmer; Sonja Gurtner; Daniel Große (FDL, 2022)

Divider Verification Using Symbolic Computer Algebra and Delayed Don't Care Optimization. - Alexander Konrad; Christoph Scholl 001; Alireza Mahzoon; Daniel Große; Rolf Drechsler (FMCAD, 2022)

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing. - Niklas Bruns; Vladimir Herdt; Daniel Große; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2022)

RVVRadar: A Framework for Supporting the Programmer in Vectorization for RISC-V. - Lucas Klemmer; Manfred Schlägl; Daniel Große (ACM Great Lakes Symposium on VLSI, 2022)

An Exploration Platform for Microcoded RISC-V Cores leveraging the One Instruction Set Computer Principle. - Lucas Klemmer; Daniel Große (ISVLSI, 2022)

RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal. - Alireza Mahzoon; Daniel Große; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Improving Design Understanding of Processors leveraging Datapath Clustering. - Katharina Ruep; Daniel Große (DATE, 2023)

Enhancing Compiler-Driven HDL Design with Automatic Waveform Analysis. - Frans Skarman; Lucas Klemmer; Oscar Gustafsson; Daniel Große (FDL, 2023)

GUI-VP Kit: A RISC-V VP Meets Linux Graphics - Enabling Interactive Graphical Application Development. - Manfred Schlägl; Daniel Große (ACM Great Lakes Symposium on VLSI, 2023)

Programming Language Assisted Waveform Analysis: A Case Study on the Instruction Performance of SERV. - Lucas Klemmer; Daniel Große (CoRR, 2023)

Verifying Embedded Graphics Libraries leveraging Virtual Prototypes and Metamorphic Testing. - Christoph Hazott; Florian Stögmüller; Daniel Große (ASPDAC, 2024)

Towards a Highly Interactive Design-Debug-Verification Cycle. - Lucas Klemmer; Daniel Große (ASPDAC, 2024)

Using Formal Verification Methods for Optimization of Circuits Under External Constraints. - Daniel Große; Lucas Klemmer; Dominik Bonora (DATE, 2024)

A RISC-V "V" VP: Unlocking Vector Processing for Evaluation at the System Level. - Manfred Schlägl; Moritz Stockinger; Daniel Große (DATE, 2024)

Relation Coverage: A New Paradigm for Hardware/Software Testing. - Christoph Hazott; Daniel Große (ETS, 2024)

An Extensible and Flexible Methodology for Analyzing the Cache Performance of Hardware Designs. - Lucas Klemmer; Daniel Große (FDL, 2024)

Single Instruction Isolation for RISC-V Vector Test Failures. - Manfred Schlägl; Daniel Große (ICCAD, 2024)

Introduction to the Special Issue on Specification and Design Languages (FDL 2021). - Julien Deantoni; Alain Girault; Daniel Große (ACM Trans. Embed. Comput. Syst., 2024)

WAVING Goodbye to Manual Waveform Analysis in HDL Design With WAL. - Lucas Klemmer; Daniel Große (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Surfer - An Extensible Waveform Viewer. - Frans Skarman; Lucas Klemmer; Daniel Große; Oscar Gustafsson; Kevin Laeufer (CAV (4), 2025)

Fast Interpreter-Based Instruction Set Simulation for Virtual Prototypes. - Manfred Schlägl; Daniel Große (DATE, 2025)

Boosting SW Development Efficiency with Function Lifetime Diagrams. - Christoph Hazott; Daniel Große (DDECS, 2025)

Refined Notions of QBF Equivalences. - Peter Pfeiffer; Daniel Große; Martina Seidl (JELIA (2), 2025)

Control Flow Protection by Cryptographic Instruction Chaining. - Shahzad Ahmad; Stefan Rass; Maksim Goman; Manfred Schlägl; Daniel Große (SECRYPT, 2025)

Using virtual prototypes and metamorphic testing to verify the hardware/software-stack of embedded graphics libraries. - Christoph Hazott; Florian Stögmüller; Daniel Große (Integr., 2025)