Design of Low Voltage Tunneling-FET Logic Circuits Considering Asymmetric Conduction Characteristics. - Daniel H. Morris; Uygar E. Avci; Rafael Rios; Ian A. Young (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

Evaluation of Low-Voltage SRAM for Error-Resilient Augmented Reality Applications. - Tony F. Wu; Doyun Kim; Daniel H. Morris; Edith Beigné (SiPS, 2021)

System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars. - Huseyin Ekin Sumbul; Tony F. Wu; Yuecheng Li; Syed Shakib Sarwar; William Koven; Eli Murphy-Trotzky; Xingxing Cai; Elnaz Ansari; Daniel H. Morris; Huichu Liu; Doyun Kim; Edith Beigné (CICC, 2022)

Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications. - Daniel H. Morris; Huichu Liu; Tony F. Wu; Huseyin Ekin Sumbul; Elnaz Ansari; Alexandre Barachant; Jonathan Reid; Edith Beigné (VLSI Technology and Circuits, 2022)

A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications. - Huseyin Ekin Sumbul; Jae-sun Seo; Daniel H. Morris; Edith Beigné (IEEE Micro, 2024)