A Self-Restored Current-Mode CMOS Multiple-Valued Logic Design Technique and its Applications. - Daniel H.-Y. Teng; Ronald J. Bolton (ISMVL, 2004)

Estimation of Average Multiple-Valued Logic Circuit Size Using Monte Carlo Simulation Technique. - Daniel H.-Y. Teng; Ronald J. Bolton (ISMVL, 2005)

A Novel Current-Mode Cmos Multiple-Valued Logic Neuron. - Daniel H.-Y. Teng (CCECE, 2006)

Convergence Analysis of Jacobi Iterative Method Using Logarithmic Number System. - Peng Huang; Daniel H.-Y. Teng; Khan A. Wahid; Seok-Bum Ko (ACIS-ICIS, 2008)

A hardware/software codesign of WZ factorization to improve time to solve matrices. - Peng Huang; Alex MacKay; Daniel H.-Y. Teng (CCECE, 2010)

FPGA based pipelined architecture for action potential simulation in biological neural systems. - Peyman Pourhaj; Daniel Hsiang-Yung Teng (CCECE, 2010)

A novel scalable parallel architecture for biological neural simulations. - Peyman Pourhaj; Daniel H.-Y. Teng; Khan A. Wahid; Seok-Bum Ko (ISCAS, 2010)

Selection Criteria of Device under Test and Their Impact on Learning Outcomes of Functional Verification. - Daniel H.-Y. Teng (TALE, 2020)