VLSI sensori-motor systems. - James J. Clark; Daniel J. Friedman (ICRA, 1991)

45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence]. - Seongwon Kim; Mohit Kapur; Mounir Meghelli; Alexander V. Rylyakov; Young Hoon Kwark; Daniel J. Friedman (CICC, 2003)

A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop. - Woogeun Rhee; Herschel A. Ainspan; Sergey V. Rylov; Alexander V. Rylyakov; Michael P. Beakes; Daniel J. Friedman; Sudhir M. Gowda; Mehmet Soyuer (CICC, 2003)

SiGe BiCMOS integrated circuits for high-speed serial communication links. - Daniel J. Friedman; Mounir Meghelli; Benjamin D. Parker; Jungwook Yang; Herschel A. Ainspan; Alexander V. Rylyakov; Young Hoon Kwark; Mark B. Ritter; Lei Shan; Steven J. Zier; Michael Sorna; Mehmet Soyuer (IBM J. Res. Dev., 2003)

A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems. - Mounir Meghelli; Alexander V. Rylyakov; Steven Zier; Michael Sorna; Daniel J. Friedman (IEEE J. Solid State Circuits, 2003)

A semi-digital delay-locked loop using an analog-based finite state machine. - Woogeun Rhee; Benjamin D. Parker; Daniel J. Friedman (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS. - Mounir Meghelli; Sergey V. Rylov; John F. Bulzacchelli; Woogeun Rhee; Alexander V. Rylyakov; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Aichin Chung; Troy J. Beukema; Petar K. Pepeljugoski; L. Shan; et al. (ISSCC, 2006)

Phase and amplitude pre-emphasis techniques for low-power serial links. - James F. Buckwalter; Mounir Meghelli; Daniel J. Friedman; Ali Hajimiri (IEEE J. Solid State Circuits, 2006)

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. - John F. Bulzacchelli; Mounir Meghelli; Sergey V. Rylov; Woogeun Rhee; Alexander V. Rylyakov; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Aichin Chung; Troy J. Beukema; Petar K. Pepeljugoski; Lei Shan; et al. (IEEE J. Solid State Circuits, 2006)

All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs. - Yong Liu 023; Woogeun Rhee; Daniel J. Friedman; Donhee Ham (ISSCC, 2007)

A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver. - Matt Park; John F. Bulzacchelli; Michael P. Beakes; Daniel J. Friedman (ISSCC, 2007)

A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI. - Alexander V. Rylyakov; José A. Tierno; George English; Daniel J. Friedman; M. Megheli (ISSCC, 2007)

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE. - Azita Emami-Neyestanak; Aida Varzaghani; John F. Bulzacchelli; Alexander V. Rylyakov; Chih-Kong Ken Yang; Daniel J. Friedman (IEEE J. Solid State Circuits, 2007)

An Ultra-Compact Differentially Tuned 6-GHz CMOS LC-VCO With Dynamic Common-Mode Feedback. - Babak Soltanian; Herschel A. Ainspan; Woogeun Rhee; Daniel J. Friedman; Peter R. Kinget (IEEE J. Solid State Circuits, 2007)

A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI. - Alexander V. Rylyakov; José A. Tierno; George English; Michael A. Sperling; Daniel J. Friedman (CICC, 2008)

A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator. - Kyu-Hyoun Kim; Paul W. Coteus; Daniel M. Dreps; Seongwon Kim; Sergey V. Rylov; Daniel J. Friedman (ISSCC, 2008)

A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS. - Alexander V. Rylyakov; José A. Tierno; Didem Zeliha Turker; Jean-Olivier Plouchart; Herschel A. Ainspan; Daniel J. Friedman (ISSCC, 2008)

A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI. - José A. Tierno; Alexander V. Rylyakov; Daniel J. Friedman (IEEE J. Solid State Circuits, 2008)

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS. - John F. Bulzacchelli; Timothy O. Dickson; Zeynep Toprak Deniz; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Sergey V. Rylov; Daniel J. Friedman (ISSCC, 2009)

A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS. - Kyu-Hyoun Kim; Daniel M. Dreps; Frank D. Ferraiolo; Paul W. Coteus; Seongwon Kim; Sergey V. Rylov; Daniel J. Friedman (ISSCC, 2009)

A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS. - Yong Liu 023; Byungsub Kim; Timothy O. Dickson; John F. Bulzacchelli; Daniel J. Friedman (ISSCC, 2009)

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications. - Alexander V. Rylyakov; José A. Tierno; Herschel A. Ainspan; Jean-Olivier Plouchart; John F. Bulzacchelli; Zeynep Toprak Deniz; Daniel J. Friedman (ISSCC, 2009)

A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology. - Timothy O. Dickson; John F. Bulzacchelli; Daniel J. Friedman (IEEE J. Solid State Circuits, 2009)

A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS. - Byungsub Kim; Yong Liu 023; Timothy O. Dickson; John F. Bulzacchelli; Daniel J. Friedman (IEEE J. Solid State Circuits, 2009)

The population health record: concepts, definition, design, and implementation. - Daniel J. Friedman; R. Gibson Parrish II (J. Am. Medical Informatics Assoc., 2010)

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. - Jae-sun Seo; Bernard Brezzo; Yong Liu 023; Benjamin D. Parker; Steven K. Esser; Robert K. Montoye; Bipin Rajendran; José A. Tierno; Leland Chang; Dharmendra S. Modha; Daniel J. Friedman (CICC, 2011)

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. - Jean-Olivier Plouchart; Mark A. Ferriss; Arun Natarajan 001; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; Aydin Babakhani; Soner Yaldiz; Lawrence T. Pileggi; Ramesh Harjani; et al. (CICC, 2012)

A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS. - Jean-Olivier Plouchart; Mihai A. T. Sanduleanu; Zeynep Toprak Deniz; Troy J. Beukema; Scott K. Reynolds; Benjamin D. Parker; Michael P. Beakes; José A. Tierno; Daniel J. Friedman (CICC, 2012)

A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS. - Ankur Agrawal; John F. Bulzacchelli; Timothy O. Dickson; Yong Liu 023; José A. Tierno; Daniel J. Friedman (ISSCC, 2012)

A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology. - John F. Bulzacchelli; Troy J. Beukema; Daniel W. Storaska; Ping-Hsuan Hsieh; Sergey V. Rylov; Daniel Furrer; Daniele Gardellini; Andrea Prati 002; Christian Menolfi; David Hanson; Juergen Hertle; Thomas Morf; et al. (ISSCC, 2012)

A compact low-power 3D I/O in 45nm CMOS. - Yong Liu 023; Wing K. Luk; Daniel J. Friedman (ISSCC, 2012)

An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. - Mark A. Ferriss; Jean-Olivier Plouchart; Arun Natarajan 001; Alexander V. Rylyakov; Benjamin D. Parker; Aydin Babakhani; Soner Yaldiz; Bodhisatwa Sadhu; Alberto Valdes-Garcia; José A. Tierno; Daniel J. Friedman (VLSIC, 2012)

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS. - Ankur Agrawal; John F. Bulzacchelli; Timothy O. Dickson; Yong Liu 023; José A. Tierno; Daniel J. Friedman (IEEE J. Solid State Circuits, 2012)

Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage. - John F. Bulzacchelli; Zeynep Toprak Deniz; Todd M. Rasmus; Joseph A. Iadanza; William L. Bucossi; Seongwon Kim; Rafael Blanco; Carrie E. Cox; Mohak Chhabra; Christopher D. LeBlanc; Christian L. Trudeau; Daniel J. Friedman (IEEE J. Solid State Circuits, 2012)

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. - John F. Bulzacchelli; Christian Menolfi; Troy J. Beukema; Daniel W. Storaska; Juergen Hertle; David Hanson; Ping-Hsuan Hsieh; Sergey V. Rylov; Daniel Furrer; Daniele Gardellini; Andrea Prati 002; Thomas Morf; et al. (IEEE J. Solid State Circuits, 2012)

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Bing Dang; Cornelia K. Tsang; Paul S. Andry; John F. Bulzacchelli; Herschel A. Ainspan; Xiaoxiong Gu; Lavanya Turlapati; Michael P. Beakes; Benjamin D. Parker; et al. (IEEE J. Solid State Circuits, 2012)

A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI. - Mihai A. T. Sanduleanu; Alberto Valdes-Garcia; Y. Liu; Benjamin D. Parker; Shlomo Shlafman; Benny Sheinman; Danny Elad; Scott K. Reynolds; Daniel J. Friedman (CICC, 2013)

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. - Shupeng Sun; Fa Wang; Soner Yaldiz; Xin Li 001; Lawrence T. Pileggi; Arun Natarajan 001; Mark A. Ferriss; Jean-Olivier Plouchart; Bodhisatwa Sadhu; Benjamin D. Parker; Alberto Valdes-Garcia; Mihai A. T. Sanduleanu; et al. (CICC, 2013)

A linearized voltage-controlled oscillator for dual-path phase-locked loops. - Glenn E. R. Cowan; Mounir Meghelli; Daniel J. Friedman (ISCAS, 2013)

A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. - Yong Liu 023; Ping-Hsuan Hsieh; Seongwon Kim; Jae-sun Seo; Robert K. Montoye; Leland Chang; José A. Tierno; Daniel J. Friedman (ISSCC, 2013)

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. - Mark A. Ferriss; Jean-Olivier Plouchart; Arun Natarajan 001; Alexander V. Rylyakov; Benjamin D. Parker; José A. Tierno; Aydin Babakhani; Soner Yaldiz; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Daniel J. Friedman (IEEE J. Solid State Circuits, 2013)

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. - Bodhisatwa Sadhu; Mark A. Ferriss; Arun Natarajan 001; Soner Yaldiz; Jean-Olivier Plouchart; Alexander V. Rylyakov; Alberto Valdes-Garcia; Benjamin D. Parker; Aydin Babakhani; Scott K. Reynolds; Xin Li 001; Lawrence T. Pileggi; et al. (IEEE J. Solid State Circuits, 2013)

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. - Jean-Olivier Plouchart; Mark A. Ferriss; Arun Natarajan 001; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; Aydin Babakhani; Soner Yaldiz; Larry T. Pileggi; Ramesh Harjani; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". - Bodhisatwa Sadhu; Mark A. Ferriss; Arun S. Natarajan 001; Soner Yaldiz; Jean-Olivier Plouchart; Alexander V. Rylyakov; Alberto Valdes-Garcia; Benjamin D. Parker; Aydin Babakhani; Scott K. Reynolds; Xin Li 001; Lawrence T. Pillage; et al. (IEEE J. Solid State Circuits, 2013)

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Ankur Agrawal; Seongwon Kim; Ping-Hsuan Hsieh; John F. Bulzacchelli; Mark A. Ferriss; Herschel A. Ainspan; Alexander V. Rylyakov; Benjamin D. Parker; Christian W. Baks; et al. (CICC, 2014)

Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with 100× Speedup in Time-to-Solution and 100, 000× Reduction in Energy-to-Solution. - Andrew S. Cassidy; Rodrigo Alvarez-Icaza; Filipp Akopyan; Jun Sawada; John V. Arthur; Paul Merolla; Pallab Datta; Marc González Tallada; Brian Taba; Alexander Andreopoulos; Arnon Amir; Steven K. Esser; et al. (SC, 2014)

Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits. - Jean-Olivier Plouchart; Fa Wang; Xin Li 001; Benjamin D. Parker; Mihai A. T. Sanduleanu; Andreea Balteanu; Bodhisatwa Sadhu; Alberto Valdes-Garcia; Daniel J. Friedman (IEEE Des. Test, 2014)

A 28 GHz Hybrid PLL in 32 nm SOI CMOS. - Mark A. Ferriss; Alexander V. Rylyakov; José A. Tierno; Herschel A. Ainspan; Daniel J. Friedman (IEEE J. Solid State Circuits, 2014)

Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. - Shupeng Sun; Fa Wang; Soner Yaldiz; Xin Li 001; Lawrence T. Pileggi; Arun Natarajan 001; Mark A. Ferriss; Jean-Olivier Plouchart; Bodhisatwa Sadhu; Benjamin D. Parker; Alberto Valdes-Garcia; Mihai A. T. Sanduleanu; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration. - Timothy O. Dickson; Yong Liu 023; Ankur Agrawal; John F. Bulzacchelli; Herschel A. Ainspan; Zeynep Toprak Deniz; Benjamin D. Parker; Mounir Meghelli; Daniel J. Friedman (CICC, 2015)

10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme. - Mark A. Ferriss; Bodhisatwa Sadhu; Alexander V. Rylyakov; Herschel A. Ainspan; Daniel J. Friedman (ISSCC, 2015)

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Ankur Agrawal; Seongwon Kim; Ping-Hsuan Hsieh; John F. Bulzacchelli; Mark A. Ferriss; Herschel A. Ainspan; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; et al. (IEEE J. Solid State Circuits, 2015)

10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs. - Mark A. Ferriss; Bodhisatwa Sadhu; Alexander V. Rylyakov; Herschel A. Ainspan; Daniel J. Friedman (ISSCC, 2016)

A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration. - Timothy O. Dickson; Yong Liu 023; Ankur Agrawal; John F. Bulzacchelli; Herschel A. Ainspan; Zeynep Toprak Deniz; Benjamin D. Parker; Michael P. Beakes; Mounir Meghelli; Daniel J. Friedman (IEEE J. Solid State Circuits, 2016)

Ultra-low-power analog design. - Daniel J. Friedman (ISSCC, 2017)

7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication. - Bodhisatwa Sadhu; Yahya M. Tousi; Joakim Hallin; Stefan Sahl; Scott K. Reynolds; Orjan Renstrom; Kristoffer Sjogren; Olov Haapalahti; Nadav Mazor; Bo Bokinge; Gustaf Weibull; Håkan Bengtsson; et al. (ISSCC, 2017)

A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications. - Bodhisatwa Sadhu; Yahya M. Tousi; Joakim Hallin; Stefan Sahl; Scott K. Reynolds; Orjan Renstrom; Kristoffer Sjogren; Olov Haapalahti; Nadav Mazor; Bo Bokinge; Gustaf Weibull; Håkan Bengtsson; et al. (IEEE J. Solid State Circuits, 2017)

Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions. - Alberto Valdes-Garcia; Bodhisatwa Sadhu; Xiaoxiong Gu; Jean-Olivier Plouchart; Mark Yeck; Daniel J. Friedman (BCICTS, 2018)

SC: Hardware approaches to machine learning and inference. - Daniel J. Friedman (ISSCC, 2018)

A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage. - Bodhisatwa Sadhu; Alberto Valdes-Garcia; Jean-Olivier Plouchart; Herschel A. Ainspan; Arpit K. Gupta; Mark A. Ferriss; Mark Yeck; Mihai Sanduleanu; Xiaoxiong Gu; Christian W. Baks; Duixian Liu; Daniel J. Friedman (IEEE J. Solid State Circuits, 2020)

24.1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology. - Alexander Fritsch; Rajiv V. Joshi; Sudipto Chakraborty; Holger Wetter; Uma Srinivasan 002; Matthew Hyde; Otto A. Torreiter; Michael Kugel; Dan Radko; Hyong Kim; Daniel J. Friedman (ISSCC, 2021)

A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation. - Kevin Tien; Ken Inoue; Scott Lekuch; David J. Frank; Sudipto Chakraborty; Pat Rosno; Thomas Fox; Mark Yeck; Joseph A. Glick; Raphael Robertazzi; Ray Richetta; John F. Bulzacchelli; et al. (DATE, 2022)

A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology. - David J. Frank; Sudipto Chakraborty; Kevin Tien; Pat Rosno; Thomas Fox; Mark Yeck; Joseph A. Glick; Raphael Robertazzi; Ray Richetta; John F. Bulzacchelli; Daniel Ramirez; Dereje Yilma; et al. (ISSCC, 2022)

A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Troy J. Beukema; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (VLSI Technology and Circuits, 2022)

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. - Serdar S. Yonar; Pier Andrea Francese; Matthias Brändli; Marcel A. Kossel; Thomas Morf; Jonathan E. Proesel; Sergey V. Rylov; Herschel A. Ainspan; Martin Cochet; Zeynep Toprak Deniz; Timothy O. Dickson; Troy J. Beukema; et al. (VLSI Technology and Circuits, 2022)

A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology. - Sudipto Chakraborty; David J. Frank; Kevin Tien; Pat Rosno; Mark Yeck; Joseph A. Glick; Raphael Robertazzi; Ray Richetta; John F. Bulzacchelli; Devin Underwood; Daniel Ramirez; Dereje Yilma; et al. (IEEE J. Solid State Circuits, 2022)

Low power cryogenic RF ASICs for quantum computing. - David J. Frank; Sudipto Chakraborty; Kevin Tien; Pat Rosno; Mark Yeck; Joseph A. Glick; Raphael Robertazzi; Ray Richetta; John F. Bulzacchelli; Daniel Ramirez; Dereje Yilma; Andrew Davies; et al. (CICC, 2023)

Cryogenic CMOS: design considerations for future quantum computing systems. - Rajiv V. Joshi; Jean-Olivier Plouchart; George Zettles; Scott Willenborg; Sudipto Chakraborty; Blake R. Johnson; Andrew Wack; Brian Allison; John Timmerwilke; Kevin Tien; Mark Yeck; Dereje Yilma; et al. (CICC, 2023)

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Troy J. Beukema; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (IEEE J. Solid State Circuits, 2023)

Characterization of 14nm CMOS Technology At Cryogenic Temperatures Using Dense Addressable Arrays. - Raphael Robertazzi; David J. Frank; Kevin Tien; John Timmerwilke; Peilin Song; Daniel J. Friedman (VTS, 2024)

Cryogenic CMOS Circuits for Future Scaled Quantum Computing Systems: Challenges and Solutions. - Bodhisatwa Sadhu; Kevin Tien; Sudipto Chakraborty; David J. Frank; Pat Rosno; Daniel Moertl; Mark Yeck; John F. Bulzacchelli; Daniil Frolov; Devin Underwood; Ken Inoue; Christian W. Baks; et al. (CICC, 2025)