Analytic Evaluation of Shared-memory Systems with ILP Processors. - Daniel J. Sorin; Vijay S. Pai; Sarita V. Adve; Mary K. Vernon; David A. Wood 001 (ISCA, 1998)

Lamport Clocks: Verifying a Directory Cache-Coherence Protocol. - Manoj Plakal; Daniel J. Sorin; Anne Condon; Mark D. Hill (SPAA, 1998)

Using Lamport Clocks to Reason about Relaxed Memory Models. - Anne Condon; Mark D. Hill; Manoj Plakal; Daniel J. Sorin (HPCA, 1999)

Multicast Snooping: A New Coherence Method Using a Multicast Address Network. - E. Ender Bilir; Ross M. Dickson; Ying Hu; Manoj Plakal; Daniel J. Sorin; Mark D. Hill; David A. Wood 001 (ISCA, 1999)

A System-Level Specification Framework for I/O Architectures. - Mark D. Hill; Anne Condon; Manoj Plakal; Daniel J. Sorin (SPAA, 1999)

Timestamp snooping: an approach for extending SMPs. - Milo M. K. Martin; Daniel J. Sorin; Anastassia Ailamaki; Alaa R. Alameldeen; Ross M. Dickson; Carl J. Mauer; Kevin E. Moore; Manoj Plakal; Mark D. Hill; David A. Wood 001 (ASPLOS, 2000)

AMVA techniques for high service time variability. - Derek L. Eager; Daniel J. Sorin; Mary K. Vernon (SIGMETRICS, 2000)

Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing. - Milo M. K. Martin; Daniel J. Sorin; Harold W. Cain; Mark D. Hill; Mikko H. Lipasti (MICRO, 2001)

Bandwidth Adaptive Snooping. - Milo M. K. Martin; Daniel J. Sorin; Mark D. Hill; David A. Wood 001 (HPCA, 2002)

SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery. - Daniel J. Sorin; Milo M. K. Martin; Mark D. Hill; David A. Wood 001 (ISCA, 2002)

Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol. - Daniel J. Sorin; Manoj Plakal; Anne Condon; Mark D. Hill; Milo M. K. Martin; David A. Wood 001 (IEEE Trans. Parallel Distributed Syst., 2002)

Dynamic Verification of End-to-End Multiprocessor Invariants. - Daniel J. Sorin; Mark D. Hill; David A. Wood 001 (DSN, 2003)

Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors. - Milo M. K. Martin; Pacia J. Harper; Daniel J. Sorin; Mark D. Hill; David A. Wood 001 (ISCA, 2003)

Quantifying instruction criticality for shared memory multiprocessors. - Tong Li 003; Alvin R. Lebeck; Daniel J. Sorin (SPAA, 2003)

Simulating a $2M Commercial Server on a $2K PC. - Alaa R. Alameldeen; Milo M. K. Martin; Carl J. Mauer; Kevin E. Moore; Min Xu; Mark D. Hill; David A. Wood 001; Daniel J. Sorin (Computer, 2003)

Analytic Evaluation of Shared-Memory Architectures. - Daniel J. Sorin; Jonathan Lemon; Derek L. Eager; Mary K. Vernon (IEEE Trans. Parallel Distributed Syst., 2003)

Tolerating Hard Faults in Microprocessor Array Structures. - Fred A. Bower; Paul G. Shealy; Sule Ozev; Daniel J. Sorin (DSN, 2004)

Using Speculation to Simplify Multiprocessor Design. - Daniel J. Sorin; Milo M. K. Martin; Mark D. Hill; David A. Wood 001 (IPDPS, 2004)

Communication breakdown: analyzing CPU usage in commercial Web workloads. - Jaidev P. Patwardhan; Alvin R. Lebeck; Daniel J. Sorin (ISPASS, 2004)

Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown. - Jonathan R. Carter; Sule Ozev; Daniel J. Sorin (DATE, 2005)

Dynamic Verification of Sequential Consistency. - Albert Meixner; Daniel J. Sorin (ISCA, 2005)

A Mechanism for Online Diagnosis of Hard Faults in Microprocessors. - Fred A. Bower; Daniel J. Sorin; Sule Ozev (MICRO, 2005)

Pulse: A Dynamic Deadlock Detection Mechanism Using Speculative Execution. - Tong Li 003; Carla Schlatter Ellis; Alvin R. Lebeck; Daniel J. Sorin (USENIX ATC, General Track, 2005)

Self-Assembled Architectures and the Temporal Aspects of Computing. - Chris Dwyer; Alvin R. Lebeck; Daniel J. Sorin (Computer, 2005)

Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. - Milo M. K. Martin; Daniel J. Sorin; Bradford M. Beckmann; Michael R. Marty; Min Xu; Alaa R. Alameldeen; Kevin E. Moore; Mark D. Hill; David A. Wood 001 (SIGARCH Comput. Archit. News, 2005)

Autonomic Microprocessor Execution via Self-Repairing Arrays. - Fred A. Bower; Sule Ozev; Daniel J. Sorin (IEEE Trans. Dependable Secur. Comput., 2005)

Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache. - Nathan Sadler; Daniel J. Sorin (ICCD, 2006)

Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier. - Mahmut Yilmaz; Derek Hower; Sule Ozev; Daniel J. Sorin (ITC, 2006)

Applying architectural vulnerability Analysis to hard faults in the microprocessor. - Fred A. Bower; Derek Hower; Mahmut Yilmaz; Daniel J. Sorin; Sule Ozev (SIGMETRICS/Performance, 2006)

NANA: A nano-scale active network architecture. - Jaidev P. Patwardhan; Chris Dwyer; Alvin R. Lebeck; Daniel J. Sorin (ACM J. Emerg. Technol. Comput. Syst., 2006)

Spin Detection Hardware for Improved Management of Multithreaded Systems. - Tong Li 003; Alvin R. Lebeck; Daniel J. Sorin (IEEE Trans. Parallel Distributed Syst., 2006)

Verification-Aware Microprocessor Design. - Anita Lungu; Daniel J. Sorin (PACT, 2007)

Error Detection Using Dynamic Dataflow Verification. - Albert Meixner; Daniel J. Sorin (PACT, 2007)

Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation. - Bogdan F. Romanescu; Michael E. Bauer; Daniel J. Sorin; Sule Ozev (PACT, 2007)

Unified microprocessor core storage. - Albert Meixner; Daniel J. Sorin (Conf. Computing Frontiers, 2007)

Lazy Error Detection for Microprocessor Functional Units. - Mahmut Yilmaz; Albert Meixner; Sule Ozev; Daniel J. Sorin (DFT, 2007)

Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures. - Albert Meixner; Daniel J. Sorin (HPCA, 2007)

Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor. - Sule Ozev; Daniel J. Sorin; Mahmut Yilmaz (ICCD, 2007)

VariaSim: simulating circuits and systems in the presence of process variability. - Bogdan F. Romanescu; Michael E. Bauer; Sule Ozev; Daniel J. Sorin (SIGARCH Comput. Archit. News, 2007)

Online diagnosis of hard faults in microprocessors. - Fred A. Bower; Daniel J. Sorin; Sule Ozev (ACM Trans. Archit. Code Optim., 2007)

Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults. - Bogdan F. Romanescu; Daniel J. Sorin (PACT, 2008)

Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching. - Bogdan F. Romanescu; Michael E. Bauer; Sule Ozev; Daniel J. Sorin (Conf. Computing Frontiers, 2008)

Detouring: Translating software to circumvent hard faults in simple cores. - Albert Meixner; Daniel J. Sorin (DSN, 2008)

The Impact of Dynamically Heterogeneous Multicore Processors on Thread Scheduling. - Fred A. Bower; Daniel J. Sorin; Landon P. Cox (IEEE Micro, 2008)

Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. - Albert Meixner; Michael E. Bauer; Daniel J. Sorin (IEEE Micro, 2008)

Reduced Precision Checking for a Floating Point Adder. - Patrick J. Eibl; Andrew D. Cook; Daniel J. Sorin (DFT, 2009)

Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms. - Meng Zhang 017; Anita Lungu; Daniel J. Sorin (DFT, 2009)

Dynamic power gating with quality guarantees. - Anita Lungu; Pradip Bose; Alper Buyuktosunoglu; Daniel J. Sorin (ISLPED, 2009)

Multicore power management: Ensuring robustness via early-stage formal verification. - Anita Lungu; Pradip Bose; Daniel J. Sorin; Steven German; Geert Janssen (MEMOCODE, 2009)

Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures. - Albert Meixner; Daniel J. Sorin (IEEE Trans. Dependable Secur. Comput., 2009)

Fault Tolerant Computer Architecture - Daniel J. Sorin (Morgan & Claypool Publishers, 2009)

Specifying and dynamically verifying address translation-aware memory consistency. - Bogdan F. Romanescu; Alvin R. Lebeck; Daniel J. Sorin (ASPLOS, 2010)

UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all. - Bogdan F. Romanescu; Alvin R. Lebeck; Daniel J. Sorin; Anne Bracy (HPCA, 2010)

Fractal Coherence: Scalably Verifiable Cache Coherence. - Meng Zhang 017; Alvin R. Lebeck; Daniel J. Sorin (MICRO, 2010)

Fractal Consistency: Architecting the Memory System to Facilitate Verification. - Meng Zhang 017; Alvin R. Lebeck; Daniel J. Sorin (IEEE Comput. Archit. Lett., 2010)

Architectures for online error detection and recovery in multicore processors. - Dimitris Gizopoulos; Mihalis Psarakis; Sarita V. Adve; Pradeep Ramachandran; Siva Kumar Sastry Hari; Daniel J. Sorin; Albert Meixner; Arijit Biswas; Xavier Vera (DATE, 2011)

An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2. - Patrick J. Eibl; Albert Meixner; Daniel J. Sorin (SIGMETRICS, 2011)

Address Translation Aware Memory Consistency. - Bogdan F. Romanescu; Alvin R. Lebeck; Daniel J. Sorin (IEEE Micro, 2011)

A Primer on Memory Consistency and Cache Coherence - Daniel J. Sorin; Mark D. Hill; David A. Wood 001 (Morgan & Claypool Publishers, 2011)

Writing cosets of a convolutional code to increase the Lifetime of Flash memory. - Adam N. Jacobvitz; A. Robert Calderbank; Daniel J. Sorin (Allerton Conference, 2012)

Why on-chip cache coherence is here to stay. - Milo M. K. Martin; Mark D. Hill; Daniel J. Sorin (Commun. ACM, 2012)

Coset coding to extend the lifetime of memory. - Adam N. Jacobvitz; A. Robert Calderbank; Daniel J. Sorin (HPCA, 2013)

Exploring memory consistency for massively-threaded throughput-oriented processors. - Blake A. Hechtman; Daniel J. Sorin (ISCA, 2013)

Evaluating cache coherent shared virtual memory for heterogeneous multicore chips. - Blake A. Hechtman; Daniel J. Sorin (ISPASS, 2013)

Applying Reduced Precision Arithmetic to Detect Errors in Floating Point Multiplication. - Kushal Seetharam; Lance Ong-Siong Co Ting Keh; Ralph Nathan; Daniel J. Sorin (PRDC, 2013)

Recycled Error Bits: Energy-Efficient Architectural Support for Higher Precision Floating Point. - Ralph Nathan; Bryan Anthonio; Shih-Lien Lu; Helia Naeimi; Daniel J. Sorin; Xiaobai Sun (CoRR, 2013)

Architecting Dynamic Power Management to be Formally Verifiable. - Daniel J. Sorin; Opeoluwa Matthews; Meng Zhang 017 (DAC, 2014)

Nostradamus: Low-cost hardware-only error detection for processor cores. - Ralph Nathan; Daniel J. Sorin (DATE, 2014)

Scalably verifiable dynamic power management. - Opeoluwa Matthews; Meng Zhang 017; Daniel J. Sorin (HPCA, 2014)

Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy. - Ralph Nathan; Bryan Anthonio; Shih-Lien Lu; Helia Naeimi; Daniel J. Sorin; Xiaobai Sun (SC, 2014)

Multi-program benchmark definition. - Adam N. Jacobvitz; Andrew D. Hilton; Daniel J. Sorin (ISPASS, 2015)

Writing without Disturb on Phase Change Memories by Integrating Coding and Layout Design. - Ali Eslami; Alfredo Velasco; Alireza Vahid; Georgios Mappouras; A. Robert Calderbank; Daniel J. Sorin (MEMSYS, 2015)

Argus-G: Comprehensive, Low-Cost Error Detection for GPGPU Cores. - Ralph Nathan; Daniel J. Sorin (IEEE Comput. Archit. Lett., 2015)

Reduced Precision Checking to Detect Errors in Floating Point Arithmetic. - Yaqi Zhang 001; Ralph Nathan; Daniel J. Sorin (CoRR, 2015)

PVCoherence: Designing Flat Coherence Protocols for Scalable Verification. - Meng Zhang 017; Jesse D. Bingham; John Erickson; Daniel J. Sorin (IEEE Micro, 2015)

Methuselah Flash: Rewriting Codes for Extra Long Storage Lifetime. - Georgios Mappouras; Alireza Vahid; A. Robert Calderbank; Daniel J. Sorin (DSN, 2016)

Verifiable hierarchical protocols with network invariants on parametric systems. - Opeoluwa Matthews; Jesse D. Bingham; Daniel J. Sorin (FMCAD, 2016)

The microarchitecture of a real-time robot motion planning accelerator. - Sean Murray; William Floyd-Jones; Ying Qi; George Dimitri Konidaris; Daniel J. Sorin (MICRO, 2016)

Robot Motion Planning on a Chip. - Sean Murray; Will Floyd-Jones; Ying Qi; Daniel J. Sorin; George Dimitri Konidaris (Robotics: Science and Systems, 2016)

TREES: A CPU/GPU Task-Parallel Runtime with Explicit Epoch Synchronization. - Blake A. Hechtman; Andrew D. Hilton; Daniel J. Sorin (CoRR, 2016)

Profile-Driven Automated Mixed Precision. - Ralph Nathan; Helia Naeimi; Daniel J. Sorin; Xiaobai Sun (CoRR, 2016)

Top Picks from the 2015 Computer Architecture Conferences. - Milo M. K. Martin; Daniel J. Sorin (IEEE Micro, 2016)

Jenga: Efficient Fault Tolerance for Stacked DRAM. - Georgios Mappouras; Alireza Vahid; A. Robert Calderbank; Derek R. Hower; Daniel J. Sorin (ICCD, 2017)

Architecting hierarchical coherence protocols for push-button parametric verification. - Opeoluwa Matthews; Daniel J. Sorin (MICRO, 2017)

Persistent Memory. - Daniel J. Sorin (Computer, 2017)

Correcting Two Deletions and Insertions in Racetrack Memory. - Alireza Vahid; Georgios Mappouras; Daniel J. Sorin; A. Robert Calderbank (CoRR, 2017)

ProtoGen: Automatically Generating Directory Cache Coherence Protocols from Atomic Specifications. - Nicolai Oswald; Vijay Nagarajan; Daniel J. Sorin (ISCA, 2018)

Low-Power Content Addressable Memory. - Daniel J. Sorin (Computer, 2018)

Extending Flash Lifetime in Embedded Processors by Expanding Analog Choice. - Georgios Mappouras; Alireza Vahid; A. Robert Calderbank; Daniel J. Sorin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Programmable Architecture for Robot Motion Planning Acceleration. - Sean Murray; Will Floyd-Jones; George Dimitri Konidaris; Daniel J. Sorin (ASAP, 2019)

GreenFlag: Protecting 3D-Racetrack Memory from Shift Errors. - Georgios Mappouras; Alireza Vahid; A. Robert Calderbank; Daniel J. Sorin (DSN, 2019)

Prospector: Synthesizing Efficient Accelerators via Statistical Learning. - Atefeh Mehrabi; Aninda Manocha; Benjamin C. Lee; Daniel J. Sorin (DATE, 2020)

Foosball Coding: Correcting Shift Errors and Bit Flip Errors in 3D Racetrack Memory. - Samantha Archer; Georgios Mappouras; A. Robert Calderbank; Daniel J. Sorin (DSN, 2020)

Roadmap Subsampling for Changing Environments. - Sean Murray; George Dimitri Konidaris; Daniel J. Sorin (IROS, 2020)

HieraGen: Automated Generation of Concurrent, Hierarchical Cache Coherence Protocols. - Nicolai Oswald; Vijay Nagarajan; Daniel J. Sorin (ISCA, 2020)

Computer Architecture for Orbital Edge Computing. - Daniel J. Sorin (Computer, 2020)

A Primer on Memory Consistency and Cache Coherence, Second Edition - Vijay Nagarajan; Daniel J. Sorin; Mark D. Hill; David A. Wood 001 (A Primer on Memory Consistency and Cache Coherence (2nd Ed.), 2020)

Learning Sparse Matrix Row Permutations for Efficient SpMM on GPU Architectures. - Atefeh Mehrabi; Donghyuk Lee; Niladrish Chatterjee; Daniel J. Sorin; Benjamin C. Lee; Mike O'Connor (ISPASS, 2021)

Reconfigurable Hardware in Postsilicon Microarchitecture. - Daniel J. Sorin (Computer, 2021)

Bayesian Optimization for Efficient Accelerator Synthesis. - Atefeh Mehrabi; Aninda Manocha; Benjamin C. Lee; Daniel J. Sorin (ACM Trans. Archit. Code Optim., 2021)

Spatiotemporal Strategies for Long-Term FPGA Resource Management. - Atefeh Mehrabi; Daniel J. Sorin; Benjamin C. Lee (ISPASS, 2022)

Rigorous Evaluation of Computer Processors with Statistical Model Checking. - Filip Mazurek; Arya Tschand; Yu Wang 044; Miroslav Pajic; Daniel J. Sorin (MICRO, 2023)

HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols. - Nicolai Oswald; Vijay Nagarajan; Daniel J. Sorin; Vasilis Gavrielatos; Theo X. Olausson; Reece Carr (IEEE Micro, 2023)

PipeGen: Automated Transformation of a Single-Core Pipeline into a Multicore Pipeline for a Given Memory Consistency Model. - An Qi Zhang; Andrés Goens; Nicolai Oswald; Tobias Grosser; Daniel J. Sorin; Vijay Nagarajan (PACT, 2024)

Determining the Minimum Number of Virtual Networks for Different Coherence Protocols. - Weihang Li; Andrés Goens; Nicolai Oswald; Vijay Nagarajan; Daniel J. Sorin (ISCA, 2024)

Low-Energy Line Codes for On-Chip Networks. - Beyza Dabak; Major Glenn; Jingyang Liu; Alexander Buck; Siyi Yang; A. Robert Calderbank; Natalie Enright Jerger; Daniel J. Sorin (CoRR, 2024)