Using a Hardware Simulation Engine for Custom MOS Structured Designs. - Zeev Barzilai; Daniel K. Beece; Leendert M. Huisman; Gabriel M. Silberman (IBM J. Res. Dev., 1984)

SLS - a fast switch level simulator for verification and fault coverage analysis. - Zeev Barzilai; Daniel K. Beece; Leendert M. Huisman; Vijay S. Iyengar; Gabriel M. Silberman (DAC, 1986)

The IBM Engineering Verification Engine. - Daniel K. Beece; George Deibert; Georgina Papp; Frank Villante (DAC, 1988)

SLS-a fast switch-level simulator [for MOS]. - Zeev Barzilai; Daniel K. Beece; Leendert M. Huisman; Vijay S. Iyengar; Gabriel M. Silberman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

The EVE companion simulator. - Daniel K. Beece; Robert F. Damiano; Georgina Papp; R. Schoen (EURO-DAC, 1990)

Design Methodology for the High-Performance G4 S/390. - Kenneth L. Shepard; Sean M. Carey; Daniel K. Beece; Robert F. Hatch; Gregory A. Northrop (ICCD, 1997)

A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders. - Charles F. Webb; Carl J. Anderson; Leon J. Sigal; Kenneth L. Shepard; John S. Liptay; James D. Warnock; Brian W. Curran; Barry Krumm; Mark D. Mayo; Peter J. Camporese; Eric M. Schwarz; Mark S. Farrell; et al. (IEEE J. Solid State Circuits, 1997)

Blue Gene: A vision for protein science using a petaflop supercomputer. - Frances E. Allen; George S. Almási; Wanda Andreoni; Daniel K. Beece; Bruce J. Berne; Arthur A. Bright; José R. Brunheroto; Calin Cascaval; José G. Castaños; Paul Coteus; Paul Crumley; Alessandro Curioni; et al. (IBM Syst. J., 2001)

Blue Gene/L, a System-On-A-Chip. - George S. Almási; Daniel K. Beece; Ralph Bellofatto; Gyan Bhanot; Randy Bickford; Matthias A. Blumrich; Arthur A. Bright; José R. Brunheroto; Calin Cascaval; José G. Castaños; Luis Ceze; Paul Coteus; et al. (CLUSTER, 2002)

An overview of the BlueGene/L Supercomputer. - Narasimha R. Adiga; George Almási 001; George S. Almási; Yariv Aridor; Rajkishore Barik; Daniel K. Beece; Ralph Bellofatto; Gyan Bhanot; Randy Bickford; Matthias A. Blumrich; Arthur A. Bright; José R. Brunheroto; et al. (SC, 2002)

Formal verification - prove it or pitch it. - Rajesh K. Gupta 001; Shishpal Rawat; Sandeep K. Shukla; Brian Bailey; Daniel K. Beece; Masahiro Fujita; Carl Pixley; John O'Leary; Fabio Somenzi (DAC, 2003)

Verification strategy for the Blue Gene/L chip. - Michael E. Wazlowski; Narasimha R. Adiga; Daniel K. Beece; Ralph Bellofatto; Matthias A. Blumrich; Dong Chen 005; Marc Boris Dombrowa; Alan Gara; Mark Giampapa; Ruud A. Haring; Philip Heidelberger; Dirk Hoenicke; et al. (IBM J. Res. Dev., 2005)

First-Order Incremental Block-Based Statistical Timing Analysis. - Chandramouli Visweswariah; K. Ravindran; Kerim Kalafala; Steven G. Walker; S. Narayan; Daniel K. Beece; Jeff Piaget; Natesan Venkateswaran; Jeffrey G. Hemmett (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Transistor sizing of custom high-performance digital circuits with parametric yield considerations. - Daniel K. Beece; Jinjun Xiong; Chandu Visweswariah; Vladimir Zolotov; Yifang Liu (DAC, 2010)