Modeling of monolithic lumped planar transformers up to 20 GHz. - Daniel Kehrer; Werner Simbürger; Hans-Dieter Wohlmuth; Arpad L. Scholtz (CICC, 2001)

A monolithic 2.45 GHz, 0.56 W power amplifier with 45% PAE at 2.4 V in standard 25 GHz fT Si-bipolar. - Winfried Bakalski; Werner Simbürger; Daniel Kehrer; Hans-Dieter Wohlmuth; Mirjana Rest; Arpad L. Scholtz (ISCAS (4), 2002)

A 20 Gb/s 82mW one-stage 4:1 multiplexer in 0.13 μm CMOS. - Daniel Kehrer; Hans-Dieter Wohlmuth (ESSCIRC, 2003)

A 15 GHz 256/257 dual-modulus prescaler in 120 nm CMOS. - Hans-Dieter Wohlmuth; Daniel Kehrer (ESSCIRC, 2003)

40-Gb/s 2: 1 multiplexer and 1: 2 demultiplexer in 120-nm standard CMOS. - Daniel Kehrer; Hans-Dieter Wohlmuth; Herbert Knapp; Martin Wurzer; Arpad L. Scholtz (IEEE J. Solid State Circuits, 2003)

A low power 13-Gb/s 2^7-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS. - Hans-Dieter Wohlmuth; Daniel Kehrer (SBCCI, 2004)

A 30-gb/s 70-mW one-stage 4: 1 multiplexer in 0.13-μm CMOS. - Daniel Kehrer; Hans-Dieter Wohlmuth (IEEE J. Solid State Circuits, 2004)

A 24 GHz dual-modulus prescaler in 90nm CMOS. - Hans-Dieter Wohlmuth; Daniel Kehrer (ISCAS (4), 2005)

Cascading Techniques for a High-Speed Memory Interface. - Zheng Gu; Peter Gregorius; Daniel Kehrer; Lydia Neumann; Evelyn Neuscheler; Thomas Rickes; Hermann Ruckerbauer; Ralf Schledz; Martin Streibl; Jürgen Zielbauer (ISSCC, 2007)

75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques. - Rex Kho; David Boursin; Martin Brox; Peter Gregorius; Heinz Hoenigschmid; Bianka Kho; Sabine Kieser; Daniel Kehrer; Maksim Kuzmenka; Udo Moeller; Pavel Veselinov Petkov; Manfred Plan; et al. (ISSCC, 2009)

A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques. - Rex Kho; David Boursin; Martin Brox; Peter Gregorius; Heinz Hoenigschmid; Bianka Kho; Sabine Kieser; Daniel Kehrer; Maksim Kuzmenka; Udo Moeller; Pavel Veselinov Petkov; Manfred Plan; et al. (IEEE J. Solid State Circuits, 2010)